Memory controller and semiconductor storage device

A memory controller that controls a memory, the memory controller comprising:

• an encoder that executes an error correction coding process based upon user data stored in the memory to generate a code word;
• and
• a decoder that executes an error correction process based upon the code word read from the memory, wherein
• the decoder includes:
• a syndrome calculating unit that calculates a syndrome based upon the code word read from the memory;
• an error locator polynomial generating unit that generates an error locator polynomial based upon the syndrome, and obtains a number of errors based upon the generated error locator polynomial;
• a plurality of error location calculating circuits, each detecting different number of bits, and each calculating an error location based upon the error locator polynomial;
• and
• a decoding control unit that selects one of the error location calculating circuits according to the number of errors.

A semiconductor storage device comprising:

• an encoder that executes an error correction coding process based upon user data stored in the memory to generate a code word;
• a memory that stores the code word;
• and
• a decoder that executes an error correction process based upon the code word read from the memory, wherein the decoder includes:
• a syndrome calculating unit that calculates a syndrome based upon the code word read from the memory;
• an error locator polynomial generating unit that generates an error locator polynomial based upon the syndrome, and obtains a number of errors based upon the generated error locator polynomial;
• an error location calculating unit that calculates an error location based upon the error locator polynomial;
• and
• a decoding control unit that control the error location calculating unit not to perform any calculation of the error location when the number of errors is not less than the maximum number of bits that can be are corrected by the error locator polynomial generating unit.