US 9,003,266 B1Granted

Pipelined turbo convolution code decoder

AssigneeXilinx, Inc.

InventorsColin Stirling, David I. Lawrie, David Andrews

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Abstract

In one embodiment, a method of block decoding is provided. For each of a plurality of data blocks input to a memory arrangement, a plurality of decoding iterations are performed using a circular pipeline of processing stages. For each decoding iteration, one processing stage of the circular pipeline performs a first set and a second set of soft-input-soft-output (SISO) decoding operations on a block of data. The first set of SISO decoding operations produces an intermediate block of data. The second set of SISO decoding operations is performed on the intermediate data block to complete the one decoding iteration. The next decoding iteration of the plurality of decoding iterations is performed using the next processing stage following the one processing stage of the circular pipeline of processing stages.

Claims20

Dependent claims

A method of decoding, comprising:

inputting a plurality of data blocks into a memory arrangement;
and
for each of the plurality of data blocks in the memory arrangement, performing a plurality of decoding iterations using a circular pipeline circuit including a plurality of processing stages, each decoding iteration including, in one processing stage of the circular pipeline circuit:
performing a first set of soft-input-soft-output (SISO) decoding operations on a block of data from the plurality of data blocks in the memory arrangement to produce an intermediate block of data;
and
performing a second set of SISO decoding operations on the intermediate data block to complete the one decoding iteration, a next decoding iteration of the plurality of decoding iterations being performed using a next processing stage following the one processing stage of the circular pipeline circuit of processing stages, one of the first and second sets of SISO decoding operations performing interleaved decoding operations and the other of the first and second sets of SISO decoding operations performing non-interleaved decoding operations;
and
in each processing stage of the circular pipeline circuit:
outputting a decoded data block in response to completing a final decoding iteration of the block of data, thereby making the next processing stage in the circular pipeline circuit available to process an unprocessed one of the plurality of data blocks, and otherwise storing a partially decoded data block in the memory arrangement in response to completing a non-final decoding iteration of the block of data;
and
inputting an unprocessed one of the plurality of data blocks into the processing stage in response to the previous processing stage in the circular pipeline circuit outputting a decoded data block, and otherwise, inputting the partially decoded data block, stored in the memory arrangement by a previous processing stage in the circular pipeline circuit, to the processing stage;
and
wherein each unprocessed data block of the plurality of data blocks is input to a respective one of the plurality of processing stages that is available to process the unprocessed data block.

10 more elements

A decoder, comprising:

a memory arrangement configured for storage of a plurality of data blocks;
a circular pipeline including a plurality of processing stages, each processing stage including:
a first processing unit coupled to the memory arrangement and configured to perform a first set of soft-input-soft-output (SISO) decoding operations on a block of data from the plurality of data blocks in the memory arrangement to produce an intermediate block of data, and store the intermediate block of data in the memory arrangement;
and
a second processing unit coupled to the memory arrangement and configured to perform a second set of SISO decoding operations using the intermediate block of data to complete one decoding iteration;
and
wherein:
each second processing unit in the processing stage is configured to output a decoded data block in response to completing a final processing iteration, thereby making the next processing stage in the circular pipeline circuit available to process an unprocessed one of the plurality of data blocks, and otherwise, store a partially decoded data block in the memory arrangement in response to completing a non-final decoding iteration of the block of data;
and
each first processing unit in the processing stage is configured to receive and process an unprocessed data block from the plurality of data blocks in the memory arrangement in response to a partially decoded data block from the second processing unit of the preceding processing stage in the circular pipeline not being available, wherein each unprocessed data block of the plurality of data blocks is received by a respective one of the plurality of processing stages that is available to process the unprocessed data block.

7 more elements

Dependencies are inferred from the claim text.