# US 9,003,256 B2 · System and method for testing integrated circuits by determining the solid timing window

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- Number: US 9,003,256 B2
- Document ID: US9003256B2
- Status: Granted
- Kind: B2
- Application number: 13/605,404
- Filed: 2012-09-06
- Published: 2013-03-07
- Granted: 2015-04-07
- Earliest claimed: 2011-09-06
- Assignees: Kingtiger Technology (Canada) Inc.
- Applicants: Bosco Chun Sang Lai; Sunny Lai-Ming Chang
- Inventors: Bosco Chun Sang Lai; Sunny Lai-Ming Chang
- Web page: https://patentgrep.com/patent/US9003256B2

## CPC

- G11C 29/50012: {of timing}
- G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, and the solid operating timing window used to determine a key timing index. A method for determining the solid operating timing window is disclosed. A plurality of sets of operating parameters is generated. For each of the plurality of sets of operating parameters, the respective set of operating parameters is applied to a test environment. The integrated circuit is then operated under the applied respective set of operating parameters. A determining a data valid window is determined for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of sets of operating parameters, where the solid operating timing window is defined as the logical intersection of the determined data valid windows such that the integrated circuit will return valid sample.

## Claims

### Claim 1

A method for testing an integrated circuit, the method comprising:
generating a plurality of sets of operating parameters;
for each of the plurality of sets of operating parameters:
applying a respective set of operating parameters to a test environment;
operating the integrated circuit in the test environment; and
determining a data valid window for the integrated circuit for the respective set of operating parameters; and
when the data valid windows have been determined for the plurality of sets of operating parameters, the data valid windows defining a set of determined data valid windows;
determining a solid operating timing window for the integrated circuit from the set of determined data valid windows whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging to the set of determined data valid windows such that the integrated circuit will return a valid sample; and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of determined data valid windows.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
determining a key timing index for the integrated circuit from the solid operating timing window, wherein the key timing index is determined by dividing the solid timing window by an ideal timing window and then multiplying by 100.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
outputting a test outcome for the integrated circuit based on the key timing index.

### Claim 4 (depends on 3)

The method of claim 3, wherein determining the data valid window comprises:
generating a plurality of test data, the plurality of test data generated by both:
a test vector pattern generate; and
tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed.

### Claim 5 (depends on 3)

The method of claim 3, wherein determining the data valid window comprises:
generating a plurality of test data, the plurality of test data generated by tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed, wherein the application system comprises a motherboard.

### Claim 6 (depends on 3)

The method of claim 3, wherein determining the data valid window comprises:
generating a plurality of test data, the plurality of test data generated by a test vector pattern generator.

### Claim 7 (depends on 3)

The method of claim 3, wherein the integrated circuit is a memory module.

### Claim 8 (depends on 3)

The method of claim 3, wherein the integrated circuit is an ASIC.

### Claim 9 (depends on 3)

The method of claim 3, wherein an operating parameter in the set of operating parameters includes at least one of temperature, voltage, frequency, and parameters associated with a motherboard.

### Claim 10

A method of testing an integrated circuit, the method comprising:
generating a plurality of sets of operating parameters;
for each of the plurality of sets of operating parameters:
applying a respective set of operating parameters to a test environment;
operating the integrated circuit in the test environment;
generating a plurality of test data;
generating a first clock signal having a first frequency and a first phase;
generating a plurality of second clock signals, each of the plurality of second clock signals having the first frequency and one of a plurality of second phases;
for each of the plurality of test data and for each of the plurality of second clock signals:
transmitting the respective test data and the first clock signal to the integrated circuit;
receiving a data signal from the integrated circuit;
capturing the data signal received from the integrated circuit in digital form by sampling the at least one data signal using the respective second clock signal of the plurality of second clock signals;
comparing the data signal when captured in digital form with a reference pattern associated with the respective test data;
determining a result from the comparing, wherein the result is associated with both the respective test data and the respective second clock signal having one of the plurality of second phases; and
identifying a data valid window for the integrated circuit for the applied set of operating parameters from the said results determined for the plurality of test data and the plurality of second clock signals; and
when the data valid windows have been identified for the plurality of sets of operating parameters, the data valid windows defining a set of identified data valid windows:
determining a solid operating timing window for the integrated circuit from the set of identified data valid windows, whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging to the set of identified data valid windows such that the integrated circuit will return a valid sample and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of identified data valid windows.

### Claim 11 (depends on 10)

The method of claim 10, further comprising: determining a key timing index for the integrated circuit from the solid operating timing window, wherein the key timing index is determined by dividing the solid timing window by an ideal timing window and then multiplying by 100.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
outputting a test outcome for the integrated circuit based on the key timing index.

### Claim 13 (depends on 12)

The method of claim 12, wherein the plurality of test data is generated by both:
a test vector pattern generator; and
tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed.

### Claim 14 (depends on 12)

The method of claim 12, wherein the plurality of test data is generated by tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed, wherein the application system comprises a motherboard.

### Claim 15 (depends on 12)

The method of claim 12, wherein the plurality of test data is generated by a test vector pattern generator.

### Claim 16 (depends on 12)

The method of claim 12, wherein the integrated circuit is a memory module.

### Claim 17 (depends on 12)

The method of claim 12, wherein the integrated circuit is an ASIC.

### Claim 18 (depends on 12)

The method of claim 12, wherein an operating parameters in the set of operating parameters includes at least one of temperature, voltage, frequency, and parameters associated with a motherboard.

### Claim 19

A system for testing an integrated circuit, the system comprising:
a test environment for operating the integrated circuit, the test environment having:
a program memory for storing instructions;
a microprocessor for retrieving instructions from the program memory, the microprocessor configured to:
instruct an operating parameter controller to apply the set of operating parameters to the test environment and send a test data to a controller; and
a controller for converting the test data between a digital form and an electrical waveform;
wherein the system is configured to:
generate a plurality of sets of operating parameters;
for each of the sets of operating parameters:
apply the respective set of operating parameters to the test environment;
operate the integrated circuit, using the test data, in the test environment; and
determine a data valid window for the integrated circuit for the set of operating parameters; and
when the data valid windows have been determined for the plurality of sets of operating parameters, the data valid windows defining a set of determined data valid windows:
determine a solid operating timing window for the integrated circuit from the set of determined data valid windows, whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging to the set of determined data valid windows such that the integrated circuit will return a valid sample, and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of determined data valid windows.

### Claim 20 (depends on 19)

The system of claim 19, wherein the system is further configured to:
determine a key timing index for the integrated circuit from the solid operating timing window, wherein the key timing index is determined by dividing the solid timing window by an ideal timing window and then multiplying by 100.

### Claim 21 (depends on 20)

The system of claim 20, wherein the system is further configured to:
output a test outcome for the integrated circuit based on the key timing index.

### Claim 22 (depends on 21)

The system of claim 21, wherein the system further comprises:
a test data source;
wherein to determine the data valid window the test data source is configured to generate a plurality of test data, the plurality of test data generated by both:
a test vector pattern generator; and
tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed.

### Claim 23 (depends on 21)

The system of claim 21, wherein the system further comprises:
a test data source;
wherein to determine the data valid window the test data source is configured to generate a plurality of test data, the plurality of test data generated by tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed, wherein the application system comprises a motherboard.

### Claim 24 (depends on 21)

The system of claim 21, wherein the system further comprises:
a test data source;
wherein to determine the data valid window the test data source is configured to generate a plurality of test data, the plurality of test data generated by a test vector pattern generator.

### Claim 25 (depends on 21)

The system of claim 21, wherein the integrated circuit is a memory module.

### Claim 26 (depends on 21)

The system of claim 21, wherein the integrated circuit is an ASIC.

### Claim 27 (depends on 21)

The system of claim 21, wherein an operating parameters in the parameters at least one of temperature, voltage, frequency, and parameters associated with a motherboard.

### Claim 28

A system for testing an integrated circuit, the system comprising:
a test environment for operating the integrated circuit, the test environment having:
a program memory for storing instructions;
a microprocessor for retrieving from the program memory, the microprocessor configured to:
instruct an operating parameter controller to apply the set of operating parameters to the test environment, and
send a test data to a controller; and
the controller for converting the test data between a digital form and an electrical waveform;
wherein the system is configured to:
generate a plurality of sets of operating parameters;
for each of the plurality of sets of operating parameters:
apply the set of operating parameters to the test environment;
operate the integrated circuit in the test environment under the set of operating parameters;
generate a plurality of test data;
generate a first clock signal having a first frequency and a first phase;
generate a plurality of second clock signals, each of the plurality of second clock signals having the first frequency and one of a plurality of second phases;
for each of the plurality of test data and for each of the plurality of second clock signals:
transmit the respective test data and the first clock signal to the integrated circuit;
receive a data signal from the integrated circuit;
capture the data signal received from the integrated circuit in digital form by sampling the at least one data signal using the respective second clock signal of the plurality of second clock signals;
compare the data signal when captured in digital form with a reference pattern associated with the respective test data;
determine a result from the comparing, wherein the result is associated with both the respective test data and the respective second clock signal having one of the plurality of second phases; and
identify a data valid window for the set of operating parameters for the integrated circuit from the said results determined for the plurality of test data and the plurality of second clock signals; and
when the data valid windows have been identified for the plurality of sets of operating parameters, the data valid windows defining a set of identified data valid windows:
determine a solid operating timing window for the integrated circuit from the set of identified data valid windows, whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging in to the set of identified data valid windows such that the integrated circuit will return a valid sample and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of identified data valid windows.

### Claim 29 (depends on 28)

The system of claim 28, wherein the system is further configured to:
determine a key timing index for the integrated circuit from the solid operating timing window, wherein the key timing index is determined by dividing the solid timing window by an ideal timing window and then multiplying by 100.

### Claim 30 (depends on 29)

The system of claim 29, wherein the system is further configured to:
output a test outcome for the integrated circuit based on the key timing index.

### Claim 31 (depends on 30)

The system of claim 30, wherein the system further comprises:
a test data source;
wherein to determine the data valid window the test data source is configured to generate a plurality of test data, the plurality of test data generated by both:
a test vector pattern generator; and
tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed.

### Claim 32 (depends on 30)

The system of claim 30, wherein the system further comprises:
a test data source;
wherein to determine the data valid window the test data source is configured to generate a plurality of test data, the plurality of test data generated by tapping application data transmitted to a reference integrated circuit provided within an application system in which an application task is performed, wherein the application system comprises a motherboard.

### Claim 33 (depends on 30)

The system of claim 30, wherein the system further comprises:
a test data source;
wherein to determine the data valid window the test data source is configured to generate a plurality of test data, the plurality of test data generated by a test vector pattern generator.

### Claim 34 (depends on 30)

The system of claim 30, wherein the integrated circuit is a memory module.

### Claim 35 (depends on 30)

The system of claim 30, wherein the integrated circuit is an ASIC.

### Claim 36 (depends on 30)

The system of claim 30, wherein an operating parameters of the set of operating parameters includes at least one of temperature, voltage, frequency, and parameters associated with a motherboard.