Method and system for memory test and repair
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorsDan Aharoni, Avichai Zalcberg, Eyal Herzog
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Abstract
Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes a memory module that includes one or more memory blocks. Each memory block includes a memory array having a first memory portion and a redundant memory portion, a failed memory indicator that, in response to a memory test, is configured to provide an indication of a failed memory portion in the first memory portion, and a wrapper circuit that, in response to the indication of the failed memory portion, is configured to repair the memory array by using the redundant portion instead of the failed memory portion.
Claims19
An integrated circuit (IC) chip, comprising:
- a memory module that includes one or more memory blocks with each memory block including:
- a memory array having a first memory portion and a redundant memory portion;
- a failed memory indicator within the memory block that, in response to a memory test, is configured to provide an indication of a failed memory portion in the first memory portion;
- a state machine configured to provide the indication of the failed memory portion;
- and
- a wrapper circuit that, in response to the indication of the failed memory portion, is configured to repair the memory array by using the redundant portion instead of the failed memory portion.
A method of repairing a memory block having a memory array including a first memory portion and a redundant memory portion, comprising:
- providing, within the memory block, an indication of a failed memory portion in the first memory portion of the memory array in response to a memory test by using a state machine of the memory array in the memory block;
- and
- repairing the memory array by using the redundant portion instead of the failed memory portion based on the indication within the memory block that is indicative of the failed memory portion.
Dependencies are inferred from the claim text.