IC test circuitry with tri-state buffer, comparator, and scan cell
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
Claims6
An integrated circuit comprising:
- A. input pads and output pads;
- B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads;
- C. test circuitry coupled between a certain output of the core circuitry and a certain output pad, the test circuitry including:
- i. a tri-state buffer having an input connected to the certain output of the core circuitry, an output coupled to the certain output pad, and an enable input;
- ii. comparator circuitry having a core input coupled to the certain output of the core circuitry, an encoded response input coupled to the certain output pad, an enable input coupled to the enable input of the tri-state buffer, and a compare output;
- and
- iii. a scan cell having a pass/fail input coupled to the compare output, a serial scan input, a boundary scan input, a serial scan output, and a serial scan control input.
Dependencies are inferred from the claim text.