US 9,003,232 B2Granted

Debug architecture

AssigneeUltraSoC Technologies Ltd.

InventorAndrew Brian Thomas Hopkins

Life of this patent

Estimating the term…

Loading patent…

Abstract

Roughly described, a method of sending a message from a source unit to a destination unit both forming part of a hierarchical debug architecture on a chip, the units in the hierarchy using a protocol in which each unit has an internal address which is the same base address, and in which each unit addresses other units using addresses derivable relative to that unit's internal address given positions of other units in the hierarchy, comprising: the source unit in a first level of the hierarchy sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address, and an intermediate unit in a second level of the hierarchy: adding an offset to the destination address to form a rebased destination address, being relative to the intermediate unit's internal address, and routing the rebased message onto the destination unit.

Claims18

Dependent claims

A method of sending a message from a source unit to a destination unit, the source unit and destination unit comprised within a plurality of units forming part of a hierarchical debug system on an integrated circuit chip, the units in the hierarchy operating according to a protocol in which each unit has the same internal address as the other units in the hierarch which is the base address, and in which each unit is configured to address other units in the hierarchy using addresses which are derivable relative to that unit's internal address given the positions of other units in the hierarchy, the method comprising:

at the source unit in a first level of the hierarchy, sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address;
and
at an intermediate unit in a second level of the hierarchy adjacent to the first level of the hierarchy:
(i) receiving the message from the source unit;
(ii) rebasing the message by adding an offset to the destination address to form a rebased destination address, the rebased destination address being relative to the intermediate unit's internal address;
and
(iii) routing the rebased message onto the destination unit.

4 more elements

An integrated circuit chip comprising:

a plurality of units forming part of a hierarchical debug system, the plurality of units in the hierarchy configured to operate according to a protocol in which each unit has the same internal address as the other units in the hierarchy which is the base address, and in which each unit is configured to address other units in the hierarchy using addresses which are derivable relative to that unit's internal address given the positions of other units in the hierarchy,
the plurality of units comprising:
a source unit in a first level of the hierarchy configured to send a message comprising a destination address of a destination unit, the destination address being relative to the source unit's internal address;
and
an intermediate unit in a second level of the hierarchy adjacent to the first level of the hierarchy configured to:
(i) receive the message from the source unit;
(ii) rebase the message by adding an offset to the destination address to form a rebased destination address, the rebased destination address being relative to the second unit's internal address;
and
(iii) route the rebased message onto the destination unit.

6 more elements

Dependencies are inferred from the claim text.