Confirming store-to-load forwards
AssigneeAdvanced Micro Devices, Inc.
InventorsMatthew A. Rafacz, Matthew M. Crum, Michael E. Tuuk
Life of this patent
Estimating the term…
Abstract
A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.
Claims25
A method to determine at a processor if a store-to-load forward operation has provided correct data to a load instruction, the method comprising:
- storing first information representing a first store instruction at a queue;
- performing the store-to-load forward operation by forwarding data of the first store instruction to the load instruction;
- retiring the first store instruction after performing the store-to-load forward operation;
- continuing to maintain the first information at the queue after performing the store-to-load forward information and the first store instruction has retired;
- and
- confirming, after the first store instruction has retired, the store-to-load forward operation based on the first information stored at the queue, wherein confirming comprises determining whether correct data was provided to the load instruction by the store-to-load forward operation.
A method comprising:
- determining that incorrect data was forwarded from a first store instruction to a load instruction by comparing an address of the load instruction to a plurality of store addresses stored at a corresponding plurality of store queue entries of a store queue, a first entry of the plurality of store queue entries indicated as storing invalid data and having a store address to which the address of the load instruction is compared;
- and
- performing a resynchronization operation at an instruction pipeline in response to the determination that incorrect data was forwarded from the first store instruction to the load instruction.
A processor comprising:
- a retire stage to retire store instructions from an instruction pipeline;
- a plurality of registers comprising a first register and a second register;
- a scheduler to perform a store-to-load forward operation by transferring data at the first register to the second register;
- and
- a load/store unit to determine if an error occurred in the store-to-load forward operation based on a retired first store instruction.
A non-transitory computer readable storage medium storing code to adapt at least one computer system to perform a portion of a process to fabricate at least part of a processor comprising:
- a retire stage to retire store instructions from an instruction pipeline;
- a plurality of registers comprising a first register and a second register;
- a scheduler to perform a store-to-load forward operation by transferring data at the first register to the second register;
- and
- a load/store unit to determine if an error occurred in the store-to-load forward operation based on a retired first store instruction.
Dependencies are inferred from the claim text.