Semiconductor integrated circuit apparatus
AssigneeRenesas Electronics Corporation
InventorHajime Yamashita
Life of this patent
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Abstract
When a bus stop request control unit issues a module-specific bus stop request signal, a bus stop control unit coupled to a bus slave determines a module that serves as a bus master of the bus slave and on which the bus slave is dependent, for example, on the basis of information in a dependence setting register. The bus stop control unit then outputs a prior bus stop request signal to the module on which the bus slave is dependent, so as to stop use of a bus of the module. Upon receipt of a module-specific bus stop completion signal indicating that processing of stop of the bus of the module on which the bus slave is dependent is complete, the bus stop control unit outputs a module-specific bus stop request signal to the module which serves as a bus slave and whose bus is to be stopped.
Claims9
A semiconductor integrated circuit apparatus comprising:
- a plurality of modules serving as bus masters;
- a module serving as a bus slave;
- and
- a bus operation control unit that, when receiving a first control signal for stopping use of a bus of the module serving as a bus slave, determines a first module serving as a bus master of the bus slave from among the modules serving as bus masters, outputs to the determined first module a second control signal for requesting stop of the bus, and after the stop of the bus by the first module is complete, outputs to the module serving as a bus slave a third control signal for requesting stop of the bus.
A semiconductor integrated circuit apparatus comprising:
- a plurality of modules serving as bus masters;
- a module serving as a bus slave;
- a storage unit that stores information for determining at least one module from among the modules serving as bus masters;
- and a bus operation control unit that, when receiving a first control signal for stopping use of a bus of the module serving as a bus slave, outputs a second control signal for requesting stop of a bus, to at least one module determined based on the information stored in the storage unit and, after receiving a signal indicating that stop of the bus is complete from all of the determined at least one module, outputs to the module serving as a bus slave a third control signal for requesting stop of the bus.
A semiconductor integrated circuit apparatus comprising:
- a plurality of first modules serving as bus masters;
- a plurality of second modules serving as bus slaves;
- a plurality of first bus stop control units disposed so as to correspond to the first modules and configured to request stop of a bus to the corresponding first modules in accordance with a first bus stop request signal;
- a plurality of second bus stop control units disposed so as to correspond to the second modules and configured to request stop of a bus to the corresponding second modules in accordance with a second bus stop request signal;
- and
- a plurality of storage units coupled to the second bus stop control units, respectively, and configured to store information for determining at least one first module from among the first modules, wherein
- upon receipt of the second bus stop request signal, each of the second bus stop control units outputs the first bus stop request signal to a first bus stop control unit corresponding to a first module determined based on information in a storage unit coupled to the second bus stop control unit and, upon receipt of a bus stop completion signal indicating that processing of stop of the bus of the determined first module is complete, from the first bus stop control unit, requests a second module corresponding to the second bus stop control unit to stop a bus.
Dependencies are inferred from the claim text.