Power-aware thread scheduling and dynamic use of processors

One or more computer storage memories comprising computer-executable instructions that, when executed by a computer, perform acts comprising:

• monitoring core activity in a multi-core system;
• retrieving a power policy for the multi-core system, the power policy balancing power savings and processing performance of individual cores in the multi-core system;
• unparking at least one core of multiple cores based at least partly on the core activity and the power policy;
• reassigning at least one thread of a plurality of threads to the at least one unparked core;
• and
• causing the at least one thread to be executed on the at least one unparked core in addition to causing one or more additional threads of the plurality of threads to be executed on one or more previously unparked cores of the multiple cores.

A multiple logical processor system, comprising:

• a plurality of processors, wherein the plurality of processors include at least one core block having multiple cores;
• and
• a controller coupled to the plurality of processors, the controller to:
• implement a performance schedule;
• implement a power savings policy;
• balance the performance schedule and the power savings policy by parking one or more cores of the multiple cores;
• and
• reassign two or more threads from the parked one or more cores to two or more unparked cores of the multiple cores.