US 9,003,171 B2 · Page fault prediction for processing vector instructions

Abstract

A system including a processor that handles a TLB miss while executing a vector read instruction in a processor is described herein. During operation, the processor performs a lookup in a TLB for addresses in active elements in the vector read instruction. The processor then determines that a TLB miss occurred for the address from an active element other than a first active element. Upon predicting that a page table walk for the vector read instruction will result in a page fault, the processor sets a bit in a corresponding bit position in an FSR. A set bit in a bit position in FSR indicates that data in a corresponding element of the vector read instruction is invalid. The processor then immediately performs memory reads for at least one of the first active element and other active elements for which TLB misses did not occur.

Claims30

Dependent claims

A method for handling a translation lookaside buffer (TLB) miss while executing a vector read instruction in a processor, comprising:

while executing the vector read instruction, performing a lookup in a TLB for addresses in active elements in the vector read instruction;
determining that a TLB miss occurred while performing the TLB lookup for the address from an active element other than a first active element;
upon predicting that a page table walk for the vector read instruction will result in a page fault, setting a bit in a corresponding bit position in a fault-status register (FSR) for the active element for which the TLB miss occurred, wherein a set bit in a bit position in the FSR indicates that data in a corresponding element of the vector read instruction is invalid;
and
performing memory reads for at least one of the first active element and other active elements for which TLB misses did not occur.

2 more elements

A processor that handles a TLB miss while executing a vector read instruction, comprising:

an execution unit in the processor, wherein the execution unit is configured to:
while executing the vector read instruction, perform a lookup in a TLB for addresses in active elements in the vector read instruction;
determine that a TLB miss occurred while performing the TLB lookup for the address from an active element other than a first active element;
upon predicting that a page table walk for the vector read instruction will result in a page fault, set a bit in a corresponding bit position in an FSR for the active element for which the TLB miss occurred, wherein a set bit in a bit position in the FSR indicates that data in a corresponding element of the vector read instruction is invalid;
and
perform memory reads for at least one of the first active element and other active elements for which TLB misses did not occur.

3 more elements

A computer system, comprising:

a processor;
a memory coupled to the processor, wherein the memory stores instructions and data for the processor;
and
an execution unit in the processor, wherein the execution unit is configured to:
while executing the vector read instruction, perform a lookup in a TLB for addresses in active elements in the vector read instruction;
determine that a TLB miss occurred while performing the TLB lookup for the address from an active element other than a first active element;
upon predicting that a page table walk for the vector read instruction will result in a page fault, set a bit in a corresponding bit position in an FSR for the active element for which the TLB miss occurred, wherein a set bit in a bit position in the FSR indicates that data in a corresponding element of the vector read instruction is invalid;
and
perform memory reads for at least one of the first active element and other active elements for which TLB misses did not occur.

6 more elements

Dependencies are inferred from the claim text.

Page fault prediction for processing vector instructions

Life of this patent

Page fault prediction for processing vector instructions

Life of this patent

Abstract

Claims30