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US 9,003,168 B1Granted
Control system for resource selection between or among conjoined-cores
AssigneeHewlett-Packard Development Company, L. P.
InventorsNorman Paul Jouppi, Parthasarathy Ranganathan
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Abstract
A processing system is provided for processing signals in a processor system including first and second conjoined-cores, and sharing a single floating point unit or a single memory interconnection network port by the first and second conjoined-cores.
Claims19
A method comprising:
- processing signals in a processor system including first and second conjoined-cores;
- and
- sharing a single memory interconnection network port for communicating signals of the first and second conjoined-cores such that the first conjoined-core issues requests through the single memory interconnection network port to a memory bank on odd cycles and the second conjoined-core issues requests to the memory bank on even cycles.
A processor system comprising:
- first and second conjoined-cores;
- and
- a single memory interconnection network port shared between the first and second conjoined-cores such that the first conjoined-core issues requests through the single memory interconnection network port to a memory bank on odd cycles and the second conjoined-core issues requests to the memory bank on even cycles.
A method comprising:
- processing signals in a processor system including first and second conjoined-cores;
- sharing a single floating point unit for processing signals of the first and second conjoined-cores;
- sharing both a L1 instruction cache and a L1 data cache between the first and second conjoined-cores;
- and
- sharing a memory interconnection network port by the first and second conjoined-cores with the first conjoined-core issuing a request to a memory bank on odd cycles and the second conjoined-core issuing a request to the memory bank on even cycles.
2 more elements
A processor system comprising:
- first and second conjoined-cores;
- a single floating point unit shared between the first and second conjoined-cores;
- and
- a memory interconnection network port shared between the first and second conjoined-cores such that the first conjoined-core issues requests through the memory interconnection network port to a memory bank on odd cycles and the second conjoined-core issues requests to the memory bank on even cycles.
1 more element
Dependencies are inferred from the claim text.