Generating hardware accelerators and processor offloads

A computer program stored on a non-transitory computer-readable media and including instructions for performing a method of automatically generating an accelerator, the method comprising:

• generating a parameter queue, directly coupled to a host processor, for receiving one or more function parameters from the host processor and allowing the queuing of accelerator tasks;
• generating a result queue, directly coupled to the host processor, for returning one or more result values to the host processor;
• generating a logic for:
• carrying out a software function in hardware,
• fetching the one or more function parameters from the parameter queue, and
• pushing the one or more result values onto the result queue;
• generating a globals port for directly accessing global variables of the software function from global memory, wherein each global variable is accessed through a global variable access state machine, and providing a first non-arbitrated direction connection from the accelerator to global memory;
• generating a globals map comprising the location of required global variables in the global memory;
• and
• generating a host port, allowing the host processor to access the accelerator, and providing a second non-arbitrated direction connection from the host processor to the accelerator.

A system for automatically generating an accelerator comprising:

• a queue generation module configured to:
• generate a parameter queue, directly coupled to a host processor, for receiving one or more function parameters from the host processor and allow the queuing of accelerator tasks;
• and
• generate a result queue, directly coupled to the host processor, for returning one or more result values to the host processor;
• a logic generation module configured to generate a logic for:
• carrying out a software function in hardware,
• fetching the one or more function parameters from the parameter queue, and
• pushing the one or more result values onto the result queue;
• a global port generation module configured to generate a global port for directly accessing global variables of the software function from global memory, wherein each global variable is accessed through a global variable access state machine, and to provide a first non-arbitrated direction connection from the accelerator to global memory;
• a map generation module configured to generate a global map comprising the location of required global variables in the global memory;
• and
• a host port generation module configured to generate a host port, to allow the host processor to access the accelerator, and to provide a second non-arbitrated direction connection from the host processor to the accelerator.

A computer implemented method of generating a hardware circuit logic block design for an accelerator automatically from software, the method comprising:

• generating a parameter queue, the parameter queue adapted for directly coupling to a host processor, and for receiving one or more function parameters from the host processor and allowing the queuing of accelerator tasks;
• generating a result queue, the result queue adapted for directly coupling to the host processor, and for returning one or more result values to the host processor;
• generating a logic, the logic adapted for:
• carrying out a software function in hardware,
• fetching the one or more function parameters from the parameter queue, and
• pushing the one or more result values onto the result queue;
• generating a globals port, the globals port adapted for directly accessing global variables of the software function from global memory, wherein each global variable is accessed through a global variable access state machine, and for providing a first non-arbitrated direction connection from the accelerator to global memory;
• generating a globals map, the globals map adapated for including the location of required global variables in the global memory;
• and
• generating a host port, the host port adapted for allowing the host processor to access the accelerator, and for providing a second non-arbitrated direction connection from the host processor to the accelerator.