Combining a remote TLB lookup and a subsequent cache miss into a single coherence operation

A shared-memory multiprocessor that reduces address-translation latency, comprising:

• a first node;
• a second node;
• and
• a coherence network that facilitates communication between the first node and the second node;
• wherein a virtual address space and a physical address space are partitioned across the two or more nodes of the shared-memory multiprocessor;
• wherein a last-level TLB structure in each node is responsible for TLB entries for a subset of the virtual address space, and wherein the last-level TLB structures of the nodes collectively form a distributed, shared last-level TLB,
• wherein, upon determining that one or more TLB levels in the first node will miss for a virtual address, the first node is configure to use the virtual address to determine a second node that is responsible for the subset of the virtual address space that includes the virtual address and send the TLB request to the second node;
• wherein the second node, upon determining a hit for the virtual address in its last-level TLB structure, is configured to ensure that a corresponding TLB entry is sent to the first node in parallel with initiating an operation to translate the virtual address into a physical address and determine whether a cache line associated with the translated physical address is available in the cache structures of any of the nodes.

A TLB structure that reduces address-translation latency in a shared-memory multiprocessor, comprising:

• a directory controller;
• and
• a distributed shared TLB structure;
• wherein a virtual address space and a physical address space are partitioned across two or more nodes of the shared-memory multiprocessor, wherein each node of the shared-memory multiprocessor comprises one or more processor cores and at least one of the TLB structure;
• wherein the distributed shared TLB structure is a last-level TLB structure that is responsible for TLB entries for a subset of the virtual address space, and wherein the last-level TLB structures of the nodes collectively form a distributed, shared last-level TLB;
• wherein a coherence network facilitates communication between a first node of the shared-memory multiprocessor and a second node of the shared-memory multiprocessor;
• wherein, upon determining that one or more TLB levels in the first node miss for a virtual address, using the virtual address to determine that the second node is responsible for the subset of the virtual address space that includes the virtual address and sending a TLB request for the virtual address to the TLB structure of the second node;
• and
• wherein the directory controller of the TLB structure of the second node, upon determining a hit for the virtual address in the distributed shared TLB structure of the second node, is configured to ensure that a corresponding TLB entry is sent to the first node in parallel with initiating an operation to translate the virtual address into a physical address and determine whether a cache line associated with the translated physical address is available in the cache structures of any of the nodes of the shared-memory multiprocessor.