Method of storing blocks of data in a plurality of memory devices in a redundant manner, a memory controller and a memory system

A memory controller for controlling the storage of a plurality of data blocks in a plurality of physically distinct non-volatile memory devices, each non-volatile memory device being independently written to or read from, wherein each of the data blocks has a logical address different from that of the others of the data blocks, and wherein at least one of the data blocks has a logical address that is outside of a sequential order of the logical addresses of the others of the data blocks, said memory controller comprising:

• a processor;
• and
• a memory storing programming code for execution by said processor, said programming code for generating one or more error checking data blocks based upon said plurality of data blocks;
• and for storing said plurality of data blocks and said one or more error checking data blocks in said plurality of physically distinct memory devices, with each of the data blocks in a different one of the physically distinct memory devices, and for linking said plurality of data blocks and said one or more error checking data blocks in an address map.

A memory controller for controlling the storage of a plurality of data blocks in a plurality of physically distinct non-volatile memory devices, each non-volatile memory device being independently written to or read from, wherein each of the data blocks has a logical address different from that of the others of the data blocks, said memory controller comprising:

• a processor;
• and
• a memory storing programming code for execution by said processor, said programming code for generating one or more error checking data blocks based upon said plurality of data blocks;
• and for storing said plurality of data blocks and said one or more error checking data blocks in said plurality of physically distinct memory devices, with each of the data blocks in a different one of the physically distinct memory devices, and for linking said plurality of data blocks and said one or more error checking data blocks in an address map;
• wherein said programming code for execution by said processor further comprises programming code for causing said processor to read one of the data blocks from one of the non-volatile memory devices at a desired address, otherwise to read others of the data blocks having addresses associated with the desired address;
• and construct the one data block pertaining to the desired address.

A memory system comprising:

• a plurality of physically distinct non-volatile memory devices, wherein each physically distinct non-volatile memory device is capable of being independently written to or read from;
• a controller for controlling the storage of a plurality of data blocks in said plurality of non-volatile memory devices wherein each of the data blocks has a logical address different from the others of the data blocks, and wherein at least one of the data blocks has a logical address that is outside of a sequential order of the logical addresses of the others of the data blocks, said controller comprising:
• a processor;
• and
• a memory storing programming code for execution by said processor, said programming code for generating one or more error checking data blocks based upon said plurality of data blocks;
• and for storing said plurality of data blocks and said one or more error checking data blocks in said plurality of physically distinct memory devices, with each of the data blocks in a different one of the physically distinct memory devices, and for linking said plurality of data blocks and said one or more error checking data blocks in an address map.

A memory system comprising:

• a plurality of physically distinct non-volatile memory devices, wherein each physically distinct non-volatile memory device is capable of being independently written to or read from;
• a controller for controlling the storage of a plurality of data blocks in said plurality of non-volatile memory devices wherein each of the data blocks has a logical address different from the others of the data blocks, said controller comprising:
• a processor;
• and
• a memory storing programming code for execution by said processor, said programming code for generating one or more error checking data blocks based upon said plurality of data blocks;
• and for storing said plurality of data blocks and said one or more error checking data blocks in said plurality of physically distinct memory devices, with each of the data blocks in a different one of the physically distinct memory devices, and for linking said plurality of data blocks and said one or more error checking data blocks in an address map;
• wherein said programming code for execution by said processor further comprises programming code for causing said processor to read one of the data blocks from one of the non-volatile memory devices at a desired address, otherwise to read others of the data blocks having addresses associated with the desired address and constructing the one data block pertaining to the desired address.

A method of operating a memory system having a plurality of physically distinct non-volatile memory devices, wherein each non-volatile memory device is capable of being independently written to or read from;

• and a controller for controlling the storage of a plurality of data blocks in said plurality of non-volatile memory devices where each of the data blocks has a logical address different from that of the others of the data blocks, said method comprising:
• writing to said memory system by:
• generating one or more error checking data blocks based upon said plurality of data blocks;
• associating addresses of said plurality of data blocks and said one or more error checking data blocks with one another;
• storing said plurality of data blocks and said one or more error checking data blocks in said plurality of physically distinct non-volatile memory devices, with each of the data blocks in a different one of the physically distinct non-volatile memory devices;
• reading from said memory system at a desired address by:
• reading one of the data blocks from one of the non-volatile memory devices having said desired address, otherwise
• reading others of the data blocks having addresses associated with said desired address and constructing the one data block pertaining to the desired address.