Multi-core processing device with invalidation cache tags and methods
AssigneeAdvanced Micro Devices, Inc.
InventorsJames O'Connor, Bradford M. Beckmann
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsJames O'Connor, Bradford M. Beckmann
Estimating the term…
A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.
A data processing device comprising:
A method of data processing comprising:
A non-transitory computer-readable storage medium storing a set of instructions for execution by a general purpose computer to facilitate manufacture of an integrated circuit that includes:
Dependencies are inferred from the claim text.