US 9,003,128 B2Granted

Cache system and processing apparatus

AssigneeKabushiki Kaisha Toshiba

InventorsKumiko Nomura, Keiko Abe, Shinobu Fujita

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Abstract

According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

Claims14

Dependent claims

A processor cache system, comprising:

a volatile cache memory included in a processor cache;
a nonvolatile cache memory included in the processor cache;
a sequence storage to store sequence data in association with each piece of data stored in the volatile cache memory, the sequence data representing the number of pieces of data stored in the nonvolatile cache memory and unused for a longer period of time than the piece of data stored in the volatile cache memory, or the number of pieces of data stored in the nonvolatile cache memory and unused for a shorter period of time than the piece of data stored in the volatile cache memory;
and
a controller to cause a first piece of data stored in the volatile cache memory to be stored in the nonvolatile cache memory when the first piece of data is overwritten by a second piece of data having another address or when power of the volatile cache memory is turned off, in a case where it is determinable based on the stored sequence data associated with the first piece of data that the first piece of data has been unused for a shorter period of time than any pieces of the data stored in the nonvolatile cache memory, or when the power of the volatile cache memory is turned off;
wherein:
line numbers of the volatile cache memory are equal to line numbers of a first LRU memory,
line numbers of the nonvolatile cache memory are equal to line numbers of a second LRU memory,
when the first piece of data is written in the cache system, the first piece of data is written in the volatile cache memory,
when the second piece of data is stored in the volatile cache memory based on a read request, the second piece of data is read from the volatile cache memory, and
when the second piece of data is only stored in the nonvolatile cache memory based on the read request, the second piece of data is read from the nonvolatile cache memory.

8 more elements

A processing apparatus, comprising a processor cache system and a processor element, wherein the cache system comprises:

a volatile cache memory included in a processor cache;
a nonvolatile cache memory included in the processor cache;
a sequence storage to store sequence data in association with each piece of data stored in the volatile cache memory, the sequence data representing the number of pieces of data stored in the nonvolatile cache memory and unused for a longer period of time than the piece of data stored in the volatile cache memory, or the number of pieces of data stored in the nonvolatile cache memory and unused for a shorter period of time than the piece of data stored in the volatile cache memory;
and
a controller to cause a first piece of data stored in the volatile cache memory to be stored in the nonvolatile cache memory when the first piece of data is overwritten by a second piece of data having another address or when power of the volatile cache memory is turned off, in a case where it is determinable based on the stored sequence data associated with the first piece of data that the first piece of data has been unused for a shorter period of time than any pieces of the data stored in the nonvolatile cache memory, or when the power of the volatile cache memory is turned off;
wherein:
line numbers of the volatile cache memory are equal to line numbers of a first LRU memory,
line numbers of the nonvolatile cache memory are equal to line numbers of a second LRU memory,
when the first piece of data is written in the cache system, the first data is written in the volatile cache memory,
when the second piece of data is stored in the volatile cache memory based on a read request, the second piece of data is read from the volatile cache memory, and
when the second piece of data is only stored in the nonvolatile cache memory based on the read request, the second piece of data is read from the nonvolatile cache memory;
and
wherein the processor element performs an operation using data to be outputted from the cache system.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/234,837Filed 16 Sep 2011
Priority: JP P2011-06527124 Mar 2011
Published: US 2012/0246412 A127 Sep 2012
Granted: 7 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/0897
Caches characterised by their organisation or structure: with two or more cache hierarchy levels
G06F 12/123
Using replacement algorithms: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 2212/225
Employing cache memory using specific memory technology: hybrid cache memory, e.g. having both volatile and non-volatile portions
Y02D 10/00
Energy efficient computing