Data processing apparatus and method for reducing storage requirements for temporary storage of data

A method of operating a data processing apparatus having processing circuitry for executing a sequence of instructions, each instruction having an associated memory address and said sequence of instructions including cacheable instructions whose associated memory addresses are within a cacheable memory region, the data processing apparatus further having an instruction cache for storing cacheable instructions for access by the processing circuitry, said instruction cache having a data storage comprising a plurality of cache lines and a tag storage comprising a plurality of tag entries, each cache line storing instruction data specifying a plurality of cacheable instructions, and each tag entry storing an address identifier for the instruction data stored in an associated cache line, the instruction cache further comprising valid flag storage for identifying for each cache line whether that cache line is valid, the method comprising:

• storing within a selected cache line of the data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, storing within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and identifying that selected cache line as valid within the valid flag storage;
• receiving data of a predetermined data type, said predetermined data type not being instruction data for a plurality of cacheable instructions;
• in response to receipt of said data of a predetermined data type, storing said data in a chosen cache line of the data storage of the instruction cache, but identifying the chosen cache line as invalid within the valid flag storage;
• and
• maintaining a record of the chosen cache line in which said data of a predetermined data type has been written, and upon receipt of a request for that data, providing that data from the instruction cache, wherein said data of a predetermined data type is instruction data for non-cacheable instructions.

A data processing apparatus comprising:

• processing means for executing a sequence of instructions, each instruction having an associated memory address and said sequence of instructions including cacheable instructions whose associated memory addresses are within a cacheable memory region;
• an instruction cache means for storing cacheable instructions for access by the processing means, said instruction cache means having a data storage means comprising a plurality of cache lines and a tag storage means comprising a plurality of tag entries, each cache line for storing instruction data specifying a plurality of cacheable instructions, and each tag entry for storing an address identifier for the instruction data stored in an associated cache line, the instruction cache means further comprising valid flag storage means for identifying for each cache line whether that cache line is valid;
• instruction cache control means for storing within a selected cache line of the data storage means the instruction data for a plurality of cacheable instructions as retrieved from memory means, for storing within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and for identifying that selected cache line as valid within the valid flag storage means;
• the instruction cache control means further for receiving data of a predetermined data type, said predetermined data type not being instruction data for a plurality of cacheable instructions;
• the instruction cache control means, responsive to receipt of said data of a predetermined data type, for storing said data in a chosen cache line of the data storage means of the instruction cache means, but for identifying the chosen cache line as invalid within the valid flag storage means;
• and
• the instruction cache control means further comprising control state means for maintaining a record of the chosen cache line in which said data of a predetermined data type has been written and, upon receipt of a request for that data, for providing that data from the instruction cache means, wherein said data of a predetermined data type is instruction data for non-cacheable instructions.