Systems and methods for non-volatile cache control

A method for controlling a cache having a volatile memory and a non-volatile memory, the method comprising:

• detecting a power loss to the cache;
• in response to the power loss detection, transitioning an information handling system (IHS) from an idle state to a backup state;
• in response to the power loss detection, automatically enabling a backup power supply associated only with the cache;
• in response to the power loss detection, a field programmable gate array (FPGA) automatically writing dirty data from the volatile memory to the non-volatile memory, the dirty data comprising data that has not been stored in a storage device;
• after writing the dirty data, transitioning the IHS from the backup state to a power down state;
• and
• upon restoration of power to the cache, the FPGA receiving a signal communicated from the non-volatile memory and the FPGA communicating the signal to a controller associated with the cache, the signal indicating presence of the dirty data in the non-volatile memory.

An information handling system (IHS), comprising:

• a processor;
• a cache coupled to the processor, comprising:
• a volatile memory;
• and
• a non-volatile memory;
• a storage device;
• a controller associated with the cache and the storage device;
• and
• a field programmable gate array (FPGA) coupled to the controller, the volatile memory, and the non-volatile memory, the FPGA configured to:
• receive a flag communicated from the non-volatile memory indicating whether the non-volatile memory includes dirty data, the dirty data comprising data that has not been stored in the storage device;
• and
• in response to the received flag:
• transition the IHS from a power up state to a restore state;
• restore the dirty data from the non-volatile memory to the volatile memory;
• communicate a first signal to the controller to flush the restored dirty data from the volatile memory to the storage device;
• and
• after detecting that the restored dirty data is flushed from the volatile memory to the storage device:
• transitioning the IHS from a restore state to an erase state;
• erasing the restored dirty data from the non-volatile memory;
• initialize the non-volatile memory for subsequent writing;
• communicate a second signal to the controller indicating the non-volatile memory is initialized;
• and
• transition the cache to a write-back mode.

An information handling system (IHS), comprising:

• a processor;
• a cache coupled to the processor, comprising:
• a volatile memory;
• and
• a non-volatile memory;
• a power supply unit coupled to the cache and associated only with the cache;
• and
• a storage device;
• a controller associated with the cache and the storage device;
• a field programmable gate array (FPGA) coupled to the controller, the volatile memory, and the non-volatile memory;
• and
• wherein the FPGA is configured to detect a power loss to the cache and in response to the power loss detection:
• transition the IHS from an idle state to a backup state;
• enable the power supply unit;
• write dirty data from the volatile memory to the non-volatile memory, the dirty data comprising data that has not been stored in the storage device;
• after writing the dirty data, transition the IHS from the backup state to a power down state;
• and
• upon restoration of power to the cache, receive a signal communicated from the non-volatile memory and communicate the signal to the controller indicating presence of the dirty data in the non-volatile memory.