Methods and apparatus providing high-speed content addressable memory (CAM) search-invalidates
AssigneeQUALCOMM Incorporated
InventorsManju Rathna Varma, David Paul Hoff, Jason Philip Martzloff
Life of this patent
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AssigneeQUALCOMM Incorporated
InventorsManju Rathna Varma, David Paul Hoff, Jason Philip Martzloff
Estimating the term…
Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.
A Content Addressable Memory (CAM) comprising:
A method of operation of a Content Addressable Memory (CAM) that comprises a CAM cell array including a plurality of CAM cells and valid bit circuitry, comprising:
A non-transitory computer-readable medium storing software for instructing a processor to:
A Content Addressable Memory (CAM) comprising:
Dependencies are inferred from the claim text.