System and method for distributed computing in non-volatile memory

A method for operating a solid state drive (SSD) having an SSD controller and a flash memory chip, the SSD controller comprising an SSD controller arithmetic logic unit (ALU), the flash memory chip including flash memory and a controller including mathematical computation functionality or logic functionality, the method comprising:

• the SSD controller receiving, via an interface configured to communicate with a host device, a write command, the write command comprising one or more values;
• responsive to receiving the write command, the SSD controller instructing the flash memory chip to store the one or more values in the flash memory;
• the SSD controller receiving a command from the host device;
• in response to receiving the command, the SSD controller sending an instruction to the flash memory chip,
• the flash memory chip, responsive to receiving the instruction, using the mathematical computation functionality or the logic functionality of the controller on the one or more values previously stored in the flash memory of the flash memory chip in order to generate one or more results;
• and
• the flash memory chip sending at least a part of the one or more results or an indication of the one or more results to the SSD controller,
• wherein the flash memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one memory layer is vertically disposed with respect to the silicon substrate.

A flash memory chip configured for use in a solid state drive (SSD), the flash memory chip comprising:

• an interface configured to communicate with an SSD controller for the SSD, the SSD controller comprising an SSD controller arithmetic logic unit (ALU) and configured to receive one or more values from a host device;
• flash memory;
• and
• a controller in communication with the interface and the memory, the controller comprising searching functionality or computation functionality, and configured to:
• receive a write command from the SSD controller, the write command indicative of writing the one or more values to the flash memory;
• in response to receiving the write command, storing the one or more values in the flash memory;
• receive a search command from the SSD controller, the search command including a data entry;
• in response to receiving the search command, use the searching functionality in order to determine whether the one or more values previously stored in the flash memory match the data entry in order to generate one or more results;
• and
• send at least a part of the one or more results or an indication of the one or more results to the SSD controller,
• wherein the flash memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one memory layer is vertically disposed with respect to the silicon substrate.

A solid state drive (SSD) comprising:

• an SSD controller comprising an SSD controller arithmetic logic unit (ALU);
• one or more memory integrated circuit chips in communication with the SSD controller, each of the one or more memory integrated circuit chips comprising:
• memory;
• and
• a memory integrated circuit chip ALU including mathematical computation functionality,
• wherein the SSD controller is configured to:
• receive a write command from the host device, the write command comprising one or more values;
• in response to receiving the write command, send a write instruction to the one or more memory integrated circuit chips to store the one or more values in the memory,
• wherein the SSD controller is further configured to:
• receive a mathematical computation command from the host device;
• responsive to receipt of the mathematical computation command, the SSD controller is configured to send a mathematical computation instruction to the one or more memory integrated circuit chips, the mathematical computation instruction being indicative to the one or more memory integrated circuit chips to perform a mathematical computation;
• wherein a respective memory integrated circuit chip is configured to:
• receive the mathematical computation instruction;
• responsive to receiving the mathematical computation instruction, the memory integrated circuit chip ALU of the respective memory integrated circuit chip is configured to perform the mathematical computation on the one or more values stored in memory locations in the memory of the respective memory integrated circuit chip in order to generate one or more results;
• and
• send at least a part of the one or more results or an indication of the one or more results to the SSD controller,
• wherein the memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one memory layer is vertically disposed with respect to the silicon substrate.

A memory integrated circuit chip configured for use in a solid state drive (SSD), the memory integrated circuit chip comprising:

• an interface configured to communicate with an SSD controller for the SSD, the SSD controller comprising an SSD controller arithmetic logic unit (ALU) and configured to receive one or more values from a host device;
• memory;
• and
• a controller in communication with the interface and the memory, the controller comprising searching functionality or computation functionality, and configured to:
• receive a write command from the SSD controller, the write command indicative of writing the one or more values to the memory;
• in response to receiving the write command, storing the one or more values in the memory;
• receive a mathematical computation instruction, the mathematical computation instruction being indicative to perform a mathematical computation;
• responsive to receiving the mathematical computation instruction, perform the mathematical computation on the one or more values in order to generate one or more results;
• and
• send at least a part of the one or more results or an indication of the one or more results to the SSD controller,
• wherein the memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one memory layer is vertically disposed with respect to the silicon substrate.