Serial interface

A method comprising:

• receiving a communication by an input pin of an IC over a single-wire bus, wherein the communication includes a command byte;
• if the command byte is an initialization command byte, performing a self-addressing operation to identify a bus address for the IC;
• and
• if the command byte is a data movement command byte, performing a data movement operation, wherein the data movement operation includes the steps of:
• if an operation address from the command byte matches the bus address, setting the bus interface of the IC from transparent mode to an_operational mode;
• accessing a register identified in the command byte;
• and
• performing data movement with the register,
• the IC having a plurality of, circuitries coupled in series from an output of the bus bus interface in a return loop to an input of the bus interface,
• wherein the bus interface is configured to assign a bus address to a first interface circuitry of the plurality of interface circuitries, and
• wherein each interface circuitry is adapted to:
• a) increment the value of a received bus address, and then convey that incremented value to a next interface circuitry and assigns that value to the next interface series-coupled interface circuitry,
• b) wherein each of the serially-coupled individually assigned interfaces is configured to receive communications from the bus in both the transparent mode and the operational mode, wherein the transparent and configurations modes are determined by comparing a communication signal to the incremented values of the received address.

A system comprising:

• a single-wire bus;
• a master controller that is coupled to the single-wire bus, wherein the controller is adapted to transmit communications over the single-wire_bus and to receive data from the bus, and wherein each communication includes a command byte;
• a plurality of slave ICs that are coupled in series with one another along the single-wire bus, wherein each slave IC includes:
• an input pin that is coupled to the single-wire bus;
• an output pin that is coupled to the single-wire bus;
• a bus interface that is coupled between the input pin and the output pin, wherein the bus interface has a transparent mode and an operational mode;
• and
• interface circuitry that is coupled to bus interface, wherein the interface circuitry is adapted to receive communications from the bus in both the transparent mode and the operational mode, and wherein the interface circuitry, upon receiving an initialization command byte, performs a self-addressing operation to identify a bus address for the IC, and wherein the interface circuitry, upon receiving a data movement command byte, sets the bus interface to operational mode, if an operation address associated with the data movement command matches the bus address, and performs a data movement,
• at least one IC having a plurality of circuitries coupled in series from an output of the bus bus interface in a return loop to an input of the bus interface,
• wherein the bus interface is configured to assign a bus address to a first interface circuitry of the plurality of interface circuitries, and
• wherein each interface circuitry is adapted to:
• a) increment the value of a received bus address, and then convey that incremented value to a next interface circuitry and assigns that value to the next interface series-coupled interface circuitry,
• b) wherein each of the serially-coupled individually assigned interfaces is configured to receive communications from the bus in both the transparent mode and the operational mode, wherein the transparent and configurations modes are determined by comparing a communication signal to the incremented values of the received address.

An apparatus comprising:

• means for receiving a communication by an input pin of an IC over a single-wire bus, wherein the communication includes a command byte;
• mean for performing a self-addressing operation to identify a bus address for the IC if the command byte is an initialization command byte;
• and
• means for performing a data movement operation if the command byte is a data movement command byte, wherein the data movement operation includes:
• means for setting the bus interface of the IC from a transparent mode to an operational mode if an operation address from the command byte matches the bus address;
• means for accessing a register identified in the command byte;
• and
• means for performing data movement with the register,
• the IC having a plurality of, circuitries coupled in series from an output of the bus bus interface in a return loop to an input of the bus interface,
• wherein the bus interface is configured to assign a bus address to a first interface circuitry of the plurality of interface circuitries, and
• wherein each interface circuitry is adapted to:
• a) increment the value of a received bus address, and then convey that incremented value to a next interface circuitry and assigns that value to the next interface series-coupled interface circuitry,
• b) wherein each of the serially-coupled individually assigned interfaces is configured to receive communications from the bus in both the transparent mode and the operational mode, wherein the transparent and configurations modes are determined by comparing a communication signal to the incremented values of the received address.

A method comprising:

• receiving a communication by an input pin for each of a plurality of ICs over a single-wire bus, wherein the communication includes a data movement command as its command byte;
• if an operation address from the command byte matches the bus address, setting a bus interface of the matched IC from a transparent mode to an operational mode;
• accessing a register in each of the plurality of ICs identified in the command byte;
• and
• performing data movement with the register for each of the plurality of ICs in an order
• the IC having a plurality of, circuitries coupled in series from an output of the bus bus interface in a return loop to an input of the bus interface,
• wherein the bus interface is configured to assign a bus address to a first interface circuitry of the plurality of interface circuitries, and
• wherein each interface circuitry is adapted to:
• a) increment the value of a received bus address, and then convey that incremented value to a next interface circuitry and assigns that value to the next interface series-coupled interface circuitry,
• b) wherein each of the serially-coupled individually assigned interfaces is configured to receive communications from the bus in both the transparent mode and the operational mode, wherein the transparent and configurations modes are determined by comparing a communication signal to the incremented values of the received address.