Circuits for shifting bussed data

A circuit for shifting bussed data, the circuit comprising:

• a first column of shift blocks, the first column shifting the bussed data by a given number of bits, the given number of bits being specified by a value of a plurality of first bits of a multi-bit shift control input;
• a first compare block that determines a value of a second bit of the multi-bit shift control input and creates an output reflecting that value;
• and
• a second column of multiplexer blocks coupled to the first column, the second column having a control input coupled to the output of the first compare block, the second column shifting the bussed data by one byte when the second bit of the multi-bit shift control input has a first value, the second column not shifting the bussed data when the second bit of the multi-bit shift control value has a second value different from the first value,
• wherein each of the shift blocks, the first compare block, and the multiplexer blocks comprises N-bit data inputs and N-bit data outputs, N being an integer greater than one, and operates on the bussed data as an N-bit bus.

A circuit for shifting bussed data, the circuit comprising:

• a bit-shift circuit having a multi-bit shift control input, an N-bit data input and an N-bit data output, the bit-shift circuit configured to shift the bussed data by a first number of bits, N being an integer greater than one, the first number being an integer less than N and specified by plurality of first bits at the multi-bit shift control input;
• a byte-shift circuit coupled to the bit-shift circuit, the byte-shift circuit having a control input, an N-bit data input and an N-bit data output, the byte-shift circuit configured to shift the bussed data by a second number of bytes in response to a value at the control input, the second number being either zero or a predetermined integer;
• a compare circuit having first and second N-bit inputs and a single-bit control output, the control output being coupled to the control input of the byte-shift circuit to control the value of the second number;
• and
• an interconnect structure comprising a plurality of N-bit busses coupled to the bit-shift circuit, the byte-shift circuit, and the compare circuit.