Wire like link for cycle reproducible and cycle accurate hardware accelerator

An apparatus for simulating a circuit design, said apparatus comprising:

• first and second field programmable gate arrays implementing, respectively, first and second blocks of the circuit design;
• at least a first clock source which drives respective states of said first and second blocks of the circuit design simulated by said first and second field programmable gate arrays at a first clock frequency;
• a wire like link configured to send a plurality of signals between said first and second field programmable gate arrays, said wire like link in turn comprising:
• a serializer, on said first field programmable gate array, to serialize said plurality of signals;
• a deserializer on said second field programmable gate array, to deserialize said plurality of signals;
• and
• a connection between said serializer and said deserializer;
• and
• at least a second clock source which clocks said serializer and said deserializer such that they operate at a second clock frequency, greater than said first clock frequency, said second clock frequency having a value such that latency of transmission and reception of said plurality of signals is less than a period corresponding to said first clock frequency.

An apparatus comprising:

• means for operating, at a first clock frequency, first and second blocks of a circuit design simulated by said first and second field programmable gate arrays, respectively;
• means for sending a plurality of signals between said first and second field programmable gate arrays via a wire like link, said wire like link comprising:
• a serializer, on said first field programmable gate array, to serialize said plurality of signals;
• a deserializer on said second field programmable gate array, to deserialize said plurality of signals;
• and
• a connection between said serializer and said deserializer;
• and
• means for operating said serializer and said deserializer at a second clock frequency, greater than said first clock frequency, said second clock frequency being selected such that latency of transmission and reception of said plurality of signals is less than a period corresponding to said first clock frequency.

A non-transitory machine readable medium embodying a design structure, the design structure embodied on the non-transitory medium in turn comprising:

• instructions which cause first and second field programmable gate arrays to implement, respectively, first and second blocks of a circuit design, said first field programmable gate array having as a macro thereon at least a portion of a serializer to serialize a plurality of signals to be sent over a wire like link between said first and second field programmable gate arrays, said second field programmable gate array having as a macro thereon at least a portion of a deserializer to deserialize said plurality of signals;
• instructions which cause said first and second field programmable gate arrays to implement at least one port for receiving a signal from at least a first clock source which drives respective states of said first and second blocks of said circuit design at a first clock frequency;
• instructions which cause said first and second field programmable gate arrays to implement at least one port for receiving a signal from at least a second clock source which clocks said serializer and said deserializer such that they operate at a second clock frequency, greater than said first clock frequency, said second clock frequency having a value such that latency of transmission and reception of said plurality of signals is less than a period corresponding to said first clock frequency.

A method comprising:

• providing a non-transitory machine readable medium embodying a design structure, the design structure embodied on the non-transitory medium in turn comprising:
• instructions which cause first and second field programmable gate arrays to implement, respectively, first and second blocks of a circuit design, said first field programmable gate array having as a macro thereon at least a portion of a serializer to serialize a plurality of signals to be sent over a wire like link between said first and second field programmable gate arrays, said second field programmable gate array having as a macro thereon at least a portion of a deserializer to deserialize said plurality of signals;
• instructions which cause said first and second field programmable gate arrays to implement at least one port for receiving a signal from at least a first clock source which drives respective states of said first and second blocks of said circuit design at a first clock frequency;
• and
• instructions which cause said first and second field programmable gate arrays to implement at least one port for receiving a signal from at least a second clock source which clocks said serializer and said deserializer such that they operate at a second clock frequency, greater than said first clock frequency, said second clock frequency having a value such that latency of transmission and reception of said plurality of signals is less than a period corresponding to said first clock frequency;
• and
• transmitting instructions corresponding to said design structure.