Method and apparatus of high speed encryption and decryption
AssigneeMarvell International Ltd.
InventorsTze Lei Poo, Siu-Hung Fred Au, Gregory Burd, David Geddes, Heng Tang
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AssigneeMarvell International Ltd.
InventorsTze Lei Poo, Siu-Hung Fred Au, Gregory Burd, David Geddes, Heng Tang
Estimating the term…
A hardware architecture for encryption and decryption device can improve the encryption and decryption data rate by using parallel processing, and pipeline operation, and save footprint by sharing hardware components. The hardware architecture can also be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit to encrypt a second portion of the array of data blocks, and a data block combiner to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks.
A decryption device configured to decrypt an array of encrypted data blocks, the decryption device comprising:
A decryption method for decrypting an array of encrypted data blocks, the method comprising:
A decryption method for decrypting an array of encrypted data blocks, the method comprising:
Dependencies are inferred from the claim text.