Techniques for transferring time information between clock domains

A circuit comprising:

• a logic circuit to generate a digital value in response to a first periodic signal;
• a first storage circuit to store time information in response to a second periodic signal, wherein the first storage circuit stores the digital value;
• a second storage circuit to store the digital value in response to the second periodic signal;
• a timing detection circuit to generate a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value stored in the first storage circuit and the digital value stored in the second storage circuit;
• and
• a compensation circuit to generate adjusted time information based on the time information stored in the first storage circuit and the detection signal.

A circuit comprising:

• a logic circuit to generate a digital value in response to a first periodic signal;
• an asynchronous first-in-first-out buffer circuit to store time information and the digital value in response to the first periodic signal, and to output the time information and the digital value in response to a second periodic signal;
• a storage circuit to store the digital value in response to the second periodic signal;
• a timing detection circuit to generate a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value stored in the storage circuit;
• and
• a compensation circuit to generate adjusted time information based on the time information stored in the asynchronous first-in-first-out buffer circuit and the detection signal.

A circuit comprising:

• a logic circuit that generates a digital signal in response to a first timing signal;
• a first storage circuit that stores time information and a value of the digital signal in response to a second timing signal;
• a second storage circuit that stores a value of the digital signal in response to the second timing signal;
• a detection circuit that generates a detection signal based on the value of the digital signal stored in the second storage circuit;
• a calculation circuit that calculates an offset signal indicating a timing difference between the first timing signal and the second timing signal based on the detection signal and based on the value of the digital signal stored in the first storage circuit;
• and
• an adjustment circuit that generates adjusted time information based on the time information stored in the first storage circuit and based on the offset signal, wherein the first timing signal and the second timing signal have different frequencies.

A method comprising:

• generating a digital signal in response to a first timing signal;
• storing time information and a value of the digital signal in a first storage circuit in response to a second timing signal;
• storing a value of the digital signal in a second storage circuit in response to the second timing signal;
• generating a detection signal based on the value of the digital signal stored in the second storage circuit;
• calculating an offset signal indicating a timing difference between the first timing signal and the second timing signal based on the detection signal and based on the value of the digital signal stored in the first storage circuit;
• and
• generating adjusted time information based on the time information stored in the first storage circuit and based on the offset signal, wherein the first timing signal and the second timing signal have different frequencies.