Digital architecture for encoding a return-to-zero differential phase shift keying waveform

A circuit for generating a return-to-zero control signal, the circuit comprising:

• an encoding block that outputs a first differential pair, including a first positive stream and a first negative stream, each representing a first data stream and a second differential pair, including a second positive stream and a second negative stream, each representing a second data stream, the first data stream including a pulse for each logical one in an input data stream, and the second data stream including a pulse for each logical zero in the input data stream;
• and
• a combining block that receives one or both of the first positive stream and first negative stream of the first differential pair and one or both of the second positive stream and second negative stream of the second differential pair and combines the received streams to generate a return-to-zero control signal for controlling a modulator, the return-to-zero control signal having a first value for representing logical ones that appear in the input data stream, a second value for representing a zero value;
• and a third value for representing logical zeros that appear in the input data stream.