Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes

A method for high-speed clock generation, the method comprising:

• receiving one or more input clock signals;
• generating a plurality of clock signals with different phase angles;
• and
• generating an output clock signal having a correct phase angle based on the plurality of clock signals by performing smoothing the plurality of clock signals with different phase angles to generate a plurality of smooth clock signals with improved linearity by using inverter-based low-pass filters.

A high-speed digital system for communication between two endpoints, the system comprising:

• a receive path configured to receive, at a first endpoint, a serial digital signal, to correct a phase of the serial digital signal using a digital device, and to generate a parallel digital signal for processing in a digital signal processor (DSP);
• and
• a transmit path configured to receive an output of the DSP and to generate a serial digital signal for transmission to a second endpoint;
• wherein the digital device comprises:
• an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate a plurality of clock signals with different phase angles;
• and
• a phase-interpolator (PI) circuit configured to receive the plurality of clock signals and to generate an output clock signal having a correct phase angle, the PI circuit comprising a smoothing block comprising inverter-based low-pass filters configured to filter harmonics of the plurality of clock signals with different phase angles and to smooth the plurality of clock signals with different phase angles to generate a plurality of smooth clock signals with improved linearity.