Semiconductor memory device and operation method thereof
AssigneeHynix Semiconductor Inc.
InventorJong-Ho Jung
Life of this patent
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Abstract
A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.
Claims13
A semiconductor memory device comprising:
- a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by a second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal;
- and
- an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation,
- wherein the delay locked loop includes a delay replica modeling unit configured to generate the feedback clock signal by delaying the DLL clock signal. wherein the output enable control circuit shares the delay replica modeling unit to generate the output enable signal.
A semiconductor memory device comprising:
- a first variable delay line configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal in response to a delay control signal;
- a reset control unit configured to generate a first reset signal and a counter enabling signal in response to a locking information;
- a second variable delay line configured to generate a second reset signal by delaying the first reset signal by a first delay time of the first variable delay line;
- a delay replica modeling unit configured to selectively delay the DLL clock signal and the second reset signal by a second time in response to the counter enabling signal to be outputted as a feedback clock signal and a third reset signal, respectively;
- a phase detection unit configured to detect a phase of the external clock signal and a phase of the feedback clock signal;
- a control signal generation unit configured to generate the delay control signal and the locking information in response to an output signal of the phase detection unit;
- a counting unit configured to generate a count value corresponding to a duration that is defined in response to the first reset signal and the third reset signal;
- and
- an output enable signal generation unit configured to generate an output enable signal in response to the count value and CAS latency information.
A method for operating a semiconductor memory device, comprising:
- delaying an input signal inputted through a set input terminal by a modeled time;
- generating a delay locked loop (DLL) clock signal by inputting the DLL clock signal to the set input terminal as the input signal in a locking operation duration;
- and
- generating an output enable signal by inputting a reset signal to the set input terminal as the input signal in an output enable signal generation duration.
A method for operating a semiconductor memory device, comprising:
- generating a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generating a feedback clock signal by delaying the DLL clock signal by the second delay time using a delay replica modeling unit included in a delay locked loop, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal;
- and
- generating an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation using the delay replica modeling unit.
Dependencies are inferred from the claim text.