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US 9,001,611 B1Granted
Three-dimensional two port register file
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Wei Wu, Jui-Che Tsai
Life of this patent
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Abstract
An integrated circuit that includes an array of memory cells. The integrated circuit also includes a write address row decoder having a plurality of write row outputs and a write address column decoder having a plurality of write column outputs. A write logic array is electrically connected to the write row outputs and the write column outputs and has a separate write word line (WWL) output electrically connected to each cell in the array of memory cells.
Claims20
An integrated circuit, comprising:
- an array of memory cells;
- a write address row decoder having a plurality of write row outputs;
- a write address column decoder having a plurality of write column outputs;
- and
- a write logic array electrically connected to the write row outputs and the write column outputs, the write logic array having a separate write word line (WWL) output electrically connected to each cell in the array of memory cells.
2 more elements
An integrated circuit, comprising:
- an array of memory cells formed on a first level;
- a write address row decoder having a plurality of write row outputs;
- a write address column decoder having a plurality of write column outputs;
- a write logic array formed on a second level different from the first level and electrically connected to the write row outputs and the write column outputs, the write logic array having a write word line (WWL) output for each cell in the array of memory cells;
- a read address row decoder having a plurality of read row outputs;
- a read address column decoder having a plurality of read column outputs;
- a read logic array formed on the second level and electrically connected to the read row outputs and the read column outputs, the read logic array having a read word line (RWL) output for each cell in array of memory cells.
4 more elements
An integrated circuit, comprising:
- an array of memory cells formed on a first level;
- a write address row decoder having a plurality of write row outputs;
- a write address column decoder having a plurality of write column outputs;
- a write logic array formed on a second level different from the first level and electrically connected to the write row outputs and the write column outputs, the write logic array having a write word line (WWL) output for each cell in the array of memory cells;
- a read address row decoder having a plurality of read row outputs;
- a read address column decoder having a plurality of read column outputs;
- a read logic array formed on the third level different from the first level and the second level and electrically connected to the read row outputs and the read column outputs, the read logic array having a read word line (RWL) output for each cell in array of memory cells.
4 more elements
Dependencies are inferred from the claim text.