Method and design for high performance non-volatile memory

A method for enabling higher data bandwidth in resistive type non-volatile random access memory circuits, the method comprising:

• synchronously latching a first serial burst having a first plurality of bits;
• storing the first plurality of bits in parallel to a first plurality of non-volatile memory cells;
• receiving a second plurality of bits in parallel stored in a second plurality of non-volatile memory cells;
• synchronously providing the second plurality of bits as a second serial burst;
• in a back-to-back burst write operation, synchronously latching a third serial burst having a third plurality of bits while the first serial burst of bits is being stored to the first plurality of non-volatile memory cells;
• and
• storing in parallel the third plurality of bits associated with the third serial burst to a third plurality of non-volatile memory cells.

A method for enabling higher data bandwidth in resistive type non-volatile random access memory circuits, the method comprising:

• synchronously latching a first serial burst having a first plurality of bits;
• storing the first plurality of bits in parallel to a first plurality of non-volatile memory cells;
• receiving a second plurality of bits in parallel stored in a second plurality of non-volatile memory cells;
• synchronously providing the second plurality of bits as a second serial burst;
• in a back-to-back burst read operation, receiving in parallel a fourth plurality of bits stored in a fourth plurality of non-volatile memory cells while the second serial burst of bits is being provided, wherein the fourth plurality of bits are associated with a fourth serial burst;
• and
• synchronously providing the fourth plurality of bits as the fourth serial burst.