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US 9,001,606 B2Granted
Memory methods and systems with adiabatic switching
AssigneeRambus Inc.
InventorsThomas Vogelsang, Brent Haukness
Life of this patent
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Abstract
A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.
Claims23
A memory comprising:
- a voltage generator to provide a varying supply voltage;
- and
- a memory core having storage cells and sense amplifiers, each sense amplifier having an N-sense supply node to receive a constant supply voltage, and a P-sense supply node coupled to the voltage generator to receive the varying supply voltage;
- a memory interface coupled to the memory core to issue memory-control signals;
- and
- timing-control circuitry coupled to the memory interface and the voltage generator, the timing-control circuitry to synchronize the varying supply voltage with the memory-control signals.
3 more elements
A method for charging a capacitive energy storage device of a memory cell from an initial voltage to a final voltage, the method comprising:
- comparing the initial voltage to a reference voltage;
- if the initial voltage is less than the reference voltage, rapidly pulling the energy storage device down to the final voltage;
- and
- if the initial voltage is greater than the reference voltage, gradually pulling the energy storage device up to the final voltage.
1 more element
An integrated circuit comprising:
- a memory core having sense amplifiers selectively coupled to bitline pairs, each sense amplifier including a P-sense supply node coupled to a varying supply voltage and an N-sense supply node coupled to a constant supply voltage;
- a memory interface coupled to the memory core to issue control signals;
- and
- timing control circuitry coupled to the memory interface to synchronize the control signals with the varying supply voltage.
1 more element
A memory comprising:
- a voltage generator to provide a varying supply voltage;
- a wordline driver coupled to the voltage generator to receive the varying supply voltage and to assert a wordline signal;
- memory cells coupled to the wordline driver via a wordline to receive the wordline signal;
- and
- timing-control circuitry coupled to the wordline driver and the voltage generator, the timing-control circuitry to synchronize the varying supply voltage with the wordline signal.
2 more elements
Dependencies are inferred from the claim text.