Systems and methods for DQS gating

A system for timing read operations with a memory device, the system comprising:

• a gating circuit configured to
• receive a timing signal from the memory device, and
• during a gating window, pass through the timing signal as a filtered timing signal, wherein the gating circuit generates the gating window based on a control signal;
• a timing control circuit configured to generate the control signal after receiving a read request from a memory controller, wherein the timing control circuit adjusts the control signal to account for temporal variations in the timing signal from the memory device;
• wherein the gating circuit comprises
• a D-type flip flop configured to receive the control signal and to output the gating window based on a timing of the control signal, and
• an “AND” gate configured to receive the gating window and the timing signal as inputs and to output the filtered timing signal.

A method for timing read operations with a memory device, the method comprising:

• receiving a timing signal from the memory device at a gating circuit;
• generating a control signal at a timing control circuit after receiving a read request from a memory controller, wherein the timing control circuit adjusts the control signal to account for temporal variations in the timing signal;
• passing through the timing signal as a filtered timing wherein the gating window is generated by the gating circuit based on the control signal;
• receiving the filtered timing signal and the control signal as inputs at a phase detector circuit;
• and
• sending a phase detect output value from the phase detector circuit to the timing control circuit based on the inputs, wherein the phase detector circuit and the timing control circuit comprise a feedback circuit.

A method for timing read operations with a memory device, the method comprising:

• receiving a timing signal from the memory device at a gating circuit;
• generating a control signal at a timing control circuit after receiving a read request from a memory controller, wherein the timing control circuit adjusts the control signal to account for temporal variations in the timing signal;
• passing through the timing signal as a filtered timing signal during a gating window, wherein the gating window is generated by the gating circuit based on the control signal;
• receiving the control signal at a D-type flip flop element of the gating circuit, wherein the flip flop element is configured to output the gating window based on a timing of the control signal;
• and
• performing an “AND” operation at an “AND” gate element of the gating circuit to output the filtered timing signal, wherein the “AND” gate is configured to receive the gating window and the timing signal as inputs for the “AND” operation.