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US 9,001,597 B2Granted
Memory system, semiconductor memory device, and wiring substrate, the semiconductor memory device including termination resistance circuit or control circuit
AssigneePS4 Luxco S.a.r.l.
InventorAtsuo Koshizuka
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first input terminal receiving a termination resistance control signal, and a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal. The termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command.
Claims14
A semiconductor device comprising:
- a first input terminal receiving a termination resistance control signal;
- and
- a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal,
- wherein the termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command, and
- wherein the semiconductor device comprises a normal operation mode in which the read command and a write command are able to be executed and a power-down mode in which execution of the read command and the write command is stopped, and on/off timings of the termination resistance circuit by the termination resistance control signal in the normal operation mode and the power-down mode are substantially the same.
2 more elements
A semiconductor device comprising:
- a control circuit including a termination control unit that is able to output a termination resistance control signal to a semiconductor memory device so as to activate an on-die-termination control circuit in the semiconductor memory device, and is able to maintain the termination resistance control signal when a read command or a write command is outputted to the semiconductor memory device,
- wherein the semiconductor device comprises a normal operation mode in which the read command and the write command are able to be executed and a power-down mode in which execution of the read command and the write command is stopped, and on/off timings of the termination resistance control si nal in the normal operation mode and the power-down mode are substantially the same.
A semiconductor device comprising:
- an embedded termination resistance connected to a data input/output terminal;
- a termination resistance control terminal that is configured to control turning on or off of said embedded termination resistance from an outside;
- and
- a termination resistance control circuit that turns off said embedded termination resistance irrespective of a level of said termination resistance control terminal when the semiconductor device outputs read data to said data input/output terminal, in response to a read command,
- wherein said semiconductor device comprises a normal operation mode in which the read command and a write command are able to be executed and a power-down mode in which execution of the read command and the write command is stopped, and on/off timings of said embedded termination resistance by the termination resistance control signal in the normal operation mode and the power-down mode are substantially the same.
2 more elements
Dependencies are inferred from the claim text.