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US 9,001,593 B2Granted
Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array
AssigneeApple Inc.
InventorsHitesh Gupta, Greg M Hess, Aravind Kandala
Life of this patent
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Abstract
A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.
Claims16
An apparatus for use in a memory array, the memory array comprising a plurality of memory elements, with each memory element comprising a read word line and a write word line, wherein each write word line is coupled to a write word line driver and each read word line is coupled to a read word line driver, the apparatus comprising:
- a predecode stage including:
- a predecode read logic configured to decode one or more read address signals and generate a plurality of predecoded read address signals;
- and
- a predecode write logic configured to decode one or more write address signals and generate a plurality of predecoded write address signals, wherein the the predecoded write address signals are generated faster than the predecoded read address signals;
- a write NAND gate of a decode stage for the memory array, wherein the write NAND gate is configured to receive the plurality of predecoded write address signals and to provide a write output signal to a write word line driver based on the write address signals, the write output signal selectively enabling the write word line driver to drive the write word line of a particular memory element for a memory write operation;
- and
- a read NAND gate of the decode stage configured to receive the plurality of predecoded read address signals and the write output signal and to provide a read output signal to a read word line driver based on the read address signals and the write output signal, wherein the read output signal selectively enables the read word line driver to drive a read word line of the particular memory element for a memory read operation, wherein the read NAND gate is further configured to enable the read word line driver only if the write output signal and the read address signals are at a logic high.
4 more elements
A device comprising:
- a memory array that includes a plurality of memory elements, wherein each memory element includes a read word line and a write word line, wherein each write word line is coupled to a write word line driver and each read word line is coupled to a read word line driver;
- predecode logic configured to decode one or more write address signals and generate a plurality of predecoded write address signals, decode one or more read address signals, and generate a plurality of predecoded read address signals, wherein the predecode logic is further configured to generate the predecoded write address signals faster than the predecoded read address signals;
- and
- decode logic comprising:
- a write NAND gate of a decode stage for the memory array, wherein the write NAND gate is configured to receive the plurality of predecoded write address signals and to provide a write output signal to a write word line driver based on the write address signals, the write output signal selectively enabling the write word line driver to drive a write word line of a particular memory element for a memory write operation;
- and
- a read NAND gate of the decode stage configured to receive the plurality of predecoded read address signals and the write output signal and to provide a read output signal to a read word line driver based on the read address signals and the write output signal, wherein the read output signal selectively enables the read word line driver to drive the read word line of the particular memory element for a memory read operation, wherein the read NAND gate is further configured to enable the read word line driver only if the write output signal and the read address signals are at a logic high.
4 more elements
A computer memory comprising:
- a plurality of memory elements, wherein each memory element includes a write word line and read word line, wherein each write word line is coupled to a write word line driver and each read word line is coupled to a read word line driver;
- predecode logic configured to decode one or more write address signals and generate a plurality of predecoded write address signals, and decode one or more read address signals and generate a plurality of predecoded read address signals, wherein the predecode logic is further configured to generate the predecoded write address signals faster than the predecoded read address signals;
- and
- decode logic comprising:
- a write NAND gate of a decode stage for the memory array, wherein the write NAND gate is configured to receive the plurality of predecoded write address signals and provide a write output signal to a write word line driver based on the write address signals, the write output signal selectively enabling the write word line driver to drive a write word line of a particular memory element for a memory write operation;
- and
- a read NAND gate of the decode stage configured to receive the plurality of predecoded read address signals and the write output signal and to provide a read output signal to a read word line driver based on the read address signals and the write output signal, wherein the read output signal selectively enables the read word line driver to drive a read word line of the particular memory element for a memory read operation, wherein the read NAND gate is further configured to enable the read word line driver only if the write output signal and the read address signals are at a logic high.
4 more elements
A method of operating a memory array, the memory array comprising a plurality of memory elements, wherein each memory element includes a write word line and a read word line, wherein each write word line is coupled to a write word line driver and each read word line is coupled to a read word line driver, wherein the method comprises:
- predecoding one or more write address signals and generating a plurality of predecoded write address signal;
- predecoding one or more read address signals and generating a plurality of predecoded read address signals;
- wherein the predecoded write address signals are generated faster than the predecoded read address signals;
- receiving, by a write NAND gate of a decode stage for the memory array, the plurality of predecoded write address signals, wherein the write NAND gate is configured to provide a write output signal to a write word line driver based on the write address signals and the write word line driver is configured to selectively drive a write word line of a particular memory element for a memory write operation based on the write output signal;
- receiving, by a read NAND gate of the decode stage, the plurality of predecoded read address signals and the write output signal, wherein the read NAND gate is configured to provide a read output signal to a read word line driver based on the read address signals and the write output signal and the read word line driver is configured to selectively drive a read word line of the particular memory element for a memory read operation based on the read output signal;
- and
- enabling, by the read NAND gate via the read output signal, the read word line driver to drive the read word line of the particular memory element for a memory read operation only if the write output signal and the read address signals are at a logic high.
4 more elements
An apparatus for use in a memory array, the memory array comprising a plurality of memory elements, wherein each memory element includes a write word line and a read word line, wherein each write word line is coupled to a write word line driver and each read word line is coupled to a read word line driver, the apparatus comprising:
- a decode stage that includes write logic for each memory element and read logic for each memory element;
- and
- a word line driver stage that includes a write word line driver and a read word line driver for each memory element;
- wherein, the write logic for a particular memory element is configured to enable the write word line driver to drive the write word line of the particular memory element for a memory write operation while prohibiting the read word line logic from enabling the read word line driver to drive the read word line of the particular memory element for a memory read operation;
- wherein the write logic is configured to enable the write word line driver to drive the write word line for the particular memory element for a memory write operation of the word line upon receiving predecoded write address signals from a predecode stage;
- wherein the read logic is configured to enable the read word line driver to enable the read word line of the particular memory element for a memory read operation of the word line upon receiving predecoded read address signals from the predecode stage unless prohibited by the write logic;
- and
- wherein upon a concurrent read from and write to the particular memory element, the write logic is configured to receive the predecoded address signals prior to the read logic receiving the predecoded address signals.
5 more elements
Dependencies are inferred from the claim text.