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US 9,001,592 B2Granted
Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorYoon Soo Jang
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device is operated by forming channels in a cell string including a plurality of memory cells and coupled between a bit line and a source line, applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively, and applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells.
Claims19
A method of operating a semiconductor memory device, the method comprising:
- forming channels in a cell string including a plurality of memory cells stacked over a substrate, wherein the cell string is coupled between a bit line and a source line;
- applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively;
- and
- applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells.
1 more element
A semiconductor memory device, comprising:
- a memory cell array including a cell string coupled between a bit line and a source line, wherein the cell string comprises a plurality of memory cells stacked over a substrate;
- a voltage generator configured to generate first and second erase voltages having different levels;
- and
- a peripheral circuit configured to form channels in the cell string and apply the first and second erase voltages to the channels through the bit line and the source line, respectively, during an erase operation.
1 more element
A method of operating a semiconductor memory device, the method comprising:
- applying a first word line voltage to at least one of a plurality of memory cells stacked between a bit line and a source line over a substrate;
- applying a second word line voltage higher than the first word line voltage to the other memory cells;
- and
- applying first and second erase voltages having different levels to channels of the plurality of memory cells through the bit line and the source line, respectively.
1 more element
Dependencies are inferred from the claim text.