Semiconductor device
AssigneeRenesas Electronics Corporation
InventorMuneaki Matsushige
Life of this patent
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Abstract
A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells, and precharge circuits (to charge the bit lines; column select signal lines extending in the column direction for selecting subarray columns; main word lines for selecting subarray rows; and precharge signal lines for supplying precharge signals to the precharge circuits; and at least two of the subarrays formed in the row direction or the column direction are controlled by the same logic according to the precharge signal.
Claims13
A semiconductor device, comprising:
- a plurality of subarrays arrayed in a matrix with row and column directions, each of the subarrays including a plurality of memory cells, bit lines coupled to the memory cells and precharge circuits configured to precharge the bit lines;
- a plurality of column select signal lines extending along a column direction to select a column of the subarrays;
- a plurality of main word lines extending along a row direction to select a row of the subarrays;
- and
- a plurality of precharge signal lines to supply a precharge signal to the precharge circuits,
- wherein at least two adjacently mounted subarrays are controlled with a same logical state in response to the precharge signal,
- wherein the subarrays controlled with the same logical state are coupled to a same precharge signal line, and
- wherein the precharge signal lines are formed as two lines each for each subarray row or column.
Dependencies are inferred from the claim text.