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US 9,001,588 B2Granted
Sense amplifier for nonvolatile semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsEui-Seung Kim, Ji-Sung Kim, SeEun O
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Abstract
A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.
Claims19
A sense amplifier circuit of a nonvolatile semiconductor memory device comprising:
- a reference voltage generator configured to output a reference voltage to a reference node depending on a current flowing through a reference data line connected to a reference bit line;
- a sensing voltage generator configured to output a sensing voltage to a sensing node depending on a current flowing through a data line connected to a bit line;
- and
- a comparator configured to sense and amplify a difference between the reference voltage of the reference node and the sensing voltage of the sensing node to detect data stored in a memory cell connected to the bit line,
- wherein the sensing voltage generator comprises:
- a first transistor connected between a power supply part and a clamping node;
- a second transistor which includes a gate and a drain connected to a gate of the first transistor and the sensing node, and a source connected to the power supply part;
- a third transistor which includes a drain connected to the drain of the second transistor;
- a fourth transistor which includes a drain-source channel connected between a source of the third transistor and a ground terminal, and a gate configured to receive a bias voltage;
- and
- an inverter configured to output an inverting output depending on a voltage of the clamping node to a gate of the third transistor.
8 more elements
A nonvolatile semiconductor memory device comprising:
- a memory cell array comprising memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines;
- a decoder configured to select a word line among the plurality of word lines and a bit line among the plurality of bit lines in the memory cell array;
- and
- a sense amplifier circuit configured to sense data stored in a memory cell among the memory cells by detecting a current flowing through the selected bit line corresponding to the memory cell,
- wherein the sense amplifier circuit comprises:
- a reference voltage generator configured to output a reference voltage to a reference node depending on a current flowing through a reference data line connected to a reference bit line;
- a sensing voltage generator configured to output a sensing voltage to a sensing node depending on a current flowing through a data line connected to the selected bit line;
- and
- a comparator configured to sense and amplify a difference between the reference voltage of the reference node and the sensing voltage of the sensing node to detect data stored in the memory cell connected to the selected bit line,
- wherein the sensing voltage generator comprises:
- a load transistor connected between a power supply part and a clamping node;
- a first PMOS transistor which includes a gate and a drain connected to the sensing node and a gate of the load transistor, and a source connected to the power supply part;
- a first NMOS transistor which includes a drain connected to the drain of the first PMOS transistor;
- and
- an inverter configured to output an inverting output depending on a voltage of the clamping node to a gate of the first NMOS transistor.
12 more elements
A sense amplifier circuit of a semiconductor memory device comprising:
- a reference voltage generator connected to a reference data line, wherein the reference voltage generator includes a current mirror having a first load transistor connected to the reference data line;
- a sensing voltage generator connected to a data line, wherein the sensing voltage generator includes a current mirror having a second load transistor connected between a power supply part and the data line;
- and
- a comparator configured to output sensing data in response to a reference voltage provided from the reference voltage generator and a sensing voltage provided from the sensing voltage generator,
- wherein the sensing voltage generator further comprises:
- a first transistor connected between a power supply part and a clamping node:
- a second transistor which includes a gate and a drain connected to a gate of the first transistor and the sensing node, and a source connected to the power supply part;
- a third transistor which includes a drain connected to the drain of the second transistor;
- a fourth transistor which includes a drain-source channel connected between a source of the third transistor and a ground terminal, and a gate configured to receive a bias voltage;
- and
- an inverter configured to output an inverting output depending on a voltage of the clamping node to a gate of the third transistor.
8 more elements
Dependencies are inferred from the claim text.