Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same
AssigneeSK hynix Inc.
InventorDeung Kak Yoo
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Abstract
A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.
Claims19
A semiconductor memory device, comprising:
- a memory cell array having a plurality of memory cells;
- a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled;
- and
- an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common,
- wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.
An erasing method of a semiconductor memory device having a plurality of memory cells and normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, the erasing method, comprising:
- providing an erase voltage to a channel of the plurality of memory cells;
- and
- gradually increasing a voltage, obtained by subtracting a voltage of the global word lines from a voltage of a block word line connected in common to gates of the normal pass transistors, while the erase voltage is provided;
- and
- applying a ground voltage to the local word lines through the global word lines.
A semiconductor memory device, comprising:
- a memory cell array having a plurality of memory cells;
- local word lines coupled to the plurality of memory cells;
- and
- an address decoder coupled to the local word lines,
- wherein the address decoder floats the local word lines to increase a voltage of the local word lines by an erase voltage provided to a channel of the plurality of memory cells, and then gradually discharges the voltage of the local word lines.
Dependencies are inferred from the claim text.