On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation

A method for performing an auto-store operation of a NVSRAM memory chip at a power-loss state, the method comprising:

• providing a low-voltage (LV) capacitor and a high-voltage (HV) capacitor formed on-chip over a NVSRAM memory chip including array of NVSRAM cells, each NVSRAM cell being made by a SRAM cell having two nodes respectively coupled to one paired Flash cell;
• charging the LV capacitor to retain up to a VDD level by coupling to a VCC power line connected to a regular VDD power supply;
• charging the HV capacitor to retain a VPP level by connecting to a positive HV charge pump circuit powered via the VCC power line;
• determining a power-loss state associated with the NVSRAM memory chip if the VCC power line connected to the regular VDD power supply is detected to drop below 80% of the VDD level;
• switching the VCC power line to the LV capacitor as a back-up power of up to the VDD level to operate each SRAM cell based on the determined power-loss state;
• applying the charged VPP level at the HV capacitor to a word line of each paired Flash cell corresponding to each SRAM cell based on the determined power-loss state, the VPP level being at least higher than a programming voltage required for inducing a FN-channel effect to write each SRAM cell logic data in the two nodes into the corresponding paired Flash cell without using any off-chip capacitors and batteries.

A VCC power system for operating an Auto-Store task of a NVSRAM memory chip, the VCC power system comprising:

• a VCC power line connected to an off-chip power supply normally for providing a VDD voltage to a NVSRAM memory chip including array of NVSRAM cells each made by a SRAM cell coupled to a paired Flash cell via at least one paired select transistor;
• a first on-chip capacitor formed on the NVSRAM memory chip, the first on-chip capacitor being charged up to the VDD voltage directly from the VCC power line;
• a second on-chip capacitor formed on the NVSRAM memory chip next to the first on-chip capacitor, the second on-chip capacitor being charged to a positive VPP voltage from an output of a high voltage (HV) pump device powered from the VCC power line;
• a VCC-level shifter including a first input connected to the VCC power line, a second input connected to the second on-chip capacitor, and a third input connected to a VCC detector configured to detect a power-loss state when voltage in the VCC power line drops below 80% of the VDD voltage;
• a VPP-level shifter sharing the first input, the second input, and the third input with the VCC-level shifter and additionally including a fourth input connected to both the second on-chip capacitor and the HV pump device;
• a VCC switch sharing the first input, the second input, and the third input with the VCC-level shifter;
• wherein the power-loss state automatically initiates switching from the first input to the second input for providing the charged VDD voltage from the first on-chip capacitor through the VCC switch to power each SRAM cell in the NVSRAM memory chip and through the VCC-level shifter to make at least the paired select transistor in conduction state connecting each SRAM cell to the corresponding paired Flash cell, and automatically applies the positive VPP voltage from the second on-chip capacitor through the VPP-level shifter to a global word line of the corresponding paired Flash cell to initiate a store operation for writing logic data of each SRAM cell into the corresponding paired Flash cell under a FN-channel scheme without erase operation.