Nonvolatile semiconductor memory device having a column decoder with multiple data bus portions connected via a switch
AssigneeKabushiki Kaisha Toshiba
InventorsTomofumi Fujimura, Naofumi Abiko
Life of this patent
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Abstract
A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch.
Claims16
A nonvolatile semiconductor memory device, comprising:
- a plurality of memory strings each including multiple memory cells;
- a plurality of word lines, each connected to a different memory cell in the plurality of memory strings;
- a plurality of bit lines, each connected to a different memory string;
- and
- a column decoder connected to the plurality of bit lines,
- wherein the column decoder includes a plurality of sense amplifiers, a plurality of data latches, and a data bus connected to and shared by the sense amplifiers and the data latches, the data bus having multiple portions including first and second portions connected through a first switch, the sense amplifiers being connected to the first portion and connected to the second portion via the first portion and the first switch, and the data latches being connected to the second portion and connected to the first portion via the second portion and the first switch.
A column decoder connected to an array of memory strings each connected by a bit line to the column decoder, comprising:
- a plurality of sense amplifier blocks;
- a plurality of data latches;
- and
- a data bus divided into a first partial data bus and a second partial data bus by a first switch and connected to and shared by the sense amplifier blocks and the data latches such that data from the sense amplifier blocks are transferred to the data latches first through the first partial data bus, and then through the first switch and the second partial data bus, and data from the data latches are transferred to the sense amplifier blocks first through the second partial data bus, and then through the first switch and the first partial data bus.
A method of controlling a column decoder having a plurality of sense amplifier blocks, a plurality of data latches, and a data bus for transferring data between sense amplifier blocks and data latches, wherein the data bus is divided into a first partial data bus and a second partial data bus, the method comprising:
- electrically disconnecting the first and second partial data buses from each other;
- precharging the second partial data bus while the sense amplifier blocks and the data latches are electrically disconnected from the second partial data bus;
- electrically connecting a first selected sense amplifier block to the second partial data bus;
- electrically connecting a corresponding data latch to the second partial data bus to store a data value provided by the first selected sense amplifier block;
- precharging the first partial data bus while the sense amplifier blocks and the data latches are electrically disconnected from the first partial data bus;
- electrically connecting a second selected sense amplifier block to the first partial data bus;
- and
- electrically connecting a corresponding data latch to the first partial data bus to store a data value provided by the second selected sense amplifier block.
Dependencies are inferred from the claim text.