Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
AssigneeSynopsys, Inc.
InventorAndrew E. Horch
Life of this patent
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Abstract
A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a gated diode device. The capacitor, transistor, and gated diode device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The gated diode device allows for erasure of an entire NVM memory more efficiently and using less substrate space than a similar device that uses a transistor. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.
Claims21
A non-volatile memory bitcell comprising:
- a gated diode device comprising:
- a first portion of a floating gate,
- an anode in a first active region of a substrate beneath the first portion of the floating gate, the anode having a doping of a first conductivity type, and
- a cathode in the first active region of the substrate beneath the first portion of the floating gate, the cathode having a doping of a second conductivity type of opposite polarity to the first conductivity type, the applying of a reverse bias band to band tunneling (BTBT) voltage to the anode or the cathode causing charge carriers to transition to the floating gate;
- a transistor comprising:
- a second portion of the floating gate,
- a source in a second active region of the substrate beneath the second portion of the floating gate, and
- a drain in the second active region, the source and drain having dopings different from each other, a current flowing between the source and drain based on a voltage level of the floating gate and a voltage difference between the source and the drain;
- and
- a capacitor comprising:
- a first plate formed in a third active region of the substrate, and
- a second plate comprising a third portion of the floating gate above the third active region, the third portion of the floating gate capacitively coupling the floating gate to the third active region to control charge carrier transition and current between the source and the drain.
A non-transitory machine readable medium that stores data representing a non-volatile memory bitcell that comprises:
- a gated diode device comprising:
- a first portion of a floating gate,
- an anode in a first active region of a substrate beneath the first portion of the floating gate, the anode having a doping of a first conductivity type, and
- a cathode in the first active region of the substrate beneath the first portion of the floating gate, the cathode having a doping of a second conductivity type of opposite polarity to the first conductivity type, the applying of a band to band tunneling (BTBT) voltage to the anode or the cathode causing charge carriers to transition to the floating gate;
- a transistor comprising:
- a second portion of the floating gate,
- a source in a second active region of the substrate beneath the second portion of the floating gate, and
- a drain in the second active region, the source and drain having dopings different from each other, a current flowing between the source and drain based on a voltage level of the floating gate and a voltage difference between the source and the drain;
- and
- a capacitor comprising:
- a first plate formed in a third active region of the substrate, and
- a second plate comprising a third portion of the floating gate above the third active region, the third portion of the floating gate capacitively coupling the floating gate to the third active region to control charge carrier transition and current between the source and the drain.
Dependencies are inferred from the claim text.