Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorChong A Hong
Life of this patent
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Abstract
A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater than or equal to the predetermined critical number, and performing an erase operation so that threshold voltages of selected memory cells are less than the set target erase level.
Claims13
A method of operating a semiconductor memory device, the method comprising:
- checking an erase-program cycling number;
- setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater than or equal to the predetermined critical number;
- and
- performing an erase operation so that threshold voltages of selected memory cells are less than the set target erase level.
A method of operating a semiconductor memory device, the method comprising:
- checking an erase-program cycling number;
- setting a target erase level to be maintained when the erase-program cycling number is less than a first predetermined critical number, setting the target erase level to be increased by a first level when the erase-program cycling number is between the first predetermined critical number and a second predetermined critical number that is greater than the first predetermined critical number, and setting the target erase level to be increased by a second level that is higher than the first level when the erase-program cycling number is greater than the second predetermined critical number;
- and
- performing an erase operation so that threshold voltages of selected memory cells are less than the set target erase level.
A semiconductor memory device, comprising:
- a memory cell array including a plurality of cell blocks storing normal data and at least one spare block storing data corresponding to an erase-program cycling number;
- and
- a peripheral circuit suitable for, when an erase operation is performed on a selected cell block among the cell blocks, setting a target erase level for the erase operation to be maintained before the erase-program cycling number reaches predetermined critical number or to be increased after the erase-program cycling number reaches the predetermined critical number, and for performing the erase operation so that threshold voltages of memory cells within the selected cell block reach the set target erase level.
Dependencies are inferred from the claim text.