System on chip including dual power rail and voltage supply method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunsu Choi, Jaeseung Choi, Gyuhong Kim, Dong-Wook Seo
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Abstract
A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.
Claims18
A system on chip, comprising:
- an SRAM including at least one memory cell and a peripheral circuit accessing the at least memory cell;
- a first power circuit configured to supply a first driving voltage to the at least one memory cell;
- and
- a second power circuit configured to supply a second driving voltage to the peripheral circuit,
- wherein the SRAM further includes an auto power switch that is configured to select the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.
A method of supplying power to an SRAM, the method comprising:
- detecting a performance mode of the SRAM, wherein the SRAM is separately supplied with a cell driving voltage that is to be supplied to a memory cell and a peripheral driving voltage that is to be supplied to a peripheral circuit configured to access the memory cell;
- comparing the cell driving voltage with the peripheral driving voltage;
- and
- selecting the cell driving voltage or the peripheral driving voltage according to a result of the comparison, wherein the selected voltage is supplied as a power supply voltage of the memory cell, the selected voltage corresponding to the higher of the cell driving voltage and the peripheral driving voltage or a voltage having substantially the same level as the cell driving voltage and the peripheral driving voltage.
A system on chip, comprising:
- a memory cell;
- a peripheral circuit configured to access the memory cell;
- a first power circuit configured to generate a first driving voltage;
- a second power circuit configured to generate a second driving voltage;
- a power controller configured to generate a performance mode signal;
- and
- an auto power switch configured to be activated or deactivated in response to the performance mode signal, wherein, when deactivated, the auto power switch is configured to supply the first driving voltage and the second driving voltage to the memory cell and the peripheral circuit, respectively, and when activated, the auto power switch is configured to supply the higher of the first driving voltage and the second driving voltage to the memory cell.
Dependencies are inferred from the claim text.