Pseudo retention till access mode enabled memory

A method of operating an SRAM in a retention till access (RTA) mode, comprising:

• generating a latched address that corresponds to an SRAM, in response to an input address bus;
• generating a flopped address in response to the latched address;
• generating a pre-decoded latched address that is provided to an RTA generation logic in response to the latched address;
• generating a pre-decoded flopped address that is provided to the RTA generation logic in response to the flopped address;
• and
• generating an RTA enable signal to activate the SRAM such that an array supply voltage of the SRAM charges one clock cycle before a memory block access.

An integrated circuit comprising:

• a processor;
• a memory coupled to the processor, the memory configurable to be used in a retention till access (RTA) mode, the memory comprising:
• an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location;
• an address flop configured to save the latched address bus and to generate a flopped address;
• a first block address pre-decoder stage configured to generate a pre-decoded latched address to a retention till access (RTA) generation logic in response to the latched address bus;
• and
• a second block address pre-decoder stage comprising a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address;
• wherein the RTA generation logic is configured to generate an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location.