US 9,001,566 B2Granted

Method for driving semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsShunpei Yamazaki, Jun Koyama, Kiyoshi Kato

Life of this patent

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Abstract

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Claims20

Dependent claims

A method for driving a semiconductor device comprising:

a first line;
a second line;
a third line;
a plurality of memory cells connected in series between the first line and the second line;
a first circuit electrically connected to the third line;
and
a second circuit electrically connected to the second line,
the method comprising a writing step and a reading step, the writing step comprising steps of:
selecting one of a plurality of writing potentials;
and
outputting the one of the plurality of writing potentials to the third line, and
the reading step comprising a step of:
supplying a potential to the first line;
and
comparing a potential of the second line and a plurality of reference potentials,
wherein each of the plurality of memory cells comprises:
a first transistor including a first gate, a first source, and a first drain;
a second transistor including a second gate, a second source, and a second drain;
and
a third transistor including a third gate, a third source, and a third drain,
wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and
wherein the first gate and one of the second source and the second drain are electrically connected to each other,
wherein the first line, the first source, and the third source are electrically connected to one another,
wherein the second line, the first drain, and the third drain are electrically connected to one another, and
wherein the third line and the other of the second source and the second drain are electrically connected to each other.

22 more elements

A method for driving a semiconductor device comprising:

a first line;
a second line;
a third line;
a plurality of memory cells connected in series between the first line and the second line;
a first circuit electrically connected to the third line;
a second circuit electrically connected to the second line;
and
a third circuit,
the method comprising a writing step and a reading step, the writing step comprising steps of:
selecting one of a plurality of writing potentials;
and
outputting the one of the plurality of writing potentials to the third line, and
the reading step comprising a step of:
selecting one of the plurality of memory cells by supplying one of a plurality of reference potentials from the third circuit;
and
detecting conductance between the first line and the second line,
wherein each of the plurality of memory cells comprises:
a first transistor having a first gate, a first source, and a first drain;
a second transistor having a second gate, a second source, and a second drain;
and
a capacitor comprising a pair of electrodes,
wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and
wherein the first gate, one of the second source and the second drain, and one of the pair of electrodes of the capacitor are electrically connected to one another,
wherein the first line and the first source are electrically connected to each other,
wherein the second line and the first drain are electrically connected to each other,
wherein the third line and the other of the second source and the second drain are electrically connected to each other, and
wherein each of the second gate and the other of the pair of electrodes of the capacitor is electrically connected to the third circuit.

24 more elements

A method for driving a semiconductor device comprising:

a first line;
a second line;
a third line;
a plurality of memory cells connected in series;
a first transistor comprising a first gate and electrically connected between the first line and the plurality of memory cells;
a second transistor comprising a second gate and electrically connected between the first line and the plurality of memory cells;
a first circuit electrically connected to the third line;
and
a second circuit electrically connected to the second line,
the method comprising a writing step and a reading step, the writing step comprising steps of:
selecting one of a plurality of writing potentials;
and
outputting the one of the plurality of writing potentials to the third line, and
the reading step comprising a step of:
supplying a first potential to the first gate and the second gate to turn on the first transistor and the second transistor,
wherein each of the plurality of memory cells comprises:
a third transistor including a third gate, a third source, and a third drain;
a fourth transistor including a fourth gate, a fourth source, and a fourth drain;
and
wherein the fourth transistor includes a channel formation region comprising an oxide semiconductor, and
wherein the third gate and one of the fourth source and the fourth drain are electrically connected to each other,
wherein the first line and the third source are electrically connected to each other through the first transistor,
wherein the second line and the third drain are electrically connected to each other through the second transistor, and
wherein the third line and the other of the fourth source are electrically connected to each other.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/186,005Filed 21 Feb 2014 · continuation
Priority: JP 2009-2555366 Nov 2009
Published: US 2014/0169100 A119 Jun 2014
Granted: 7 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell

Family

Application12/917,564Parent of this continuation · filed 2 Nov 2010
Application13/749,961Parent of this continuation · filed 25 Jan 2013
US 8,363,452 B2Parent of this continuation · filed 29 Jan 2013
US 2014/0169100 A1Pre-grant publication · published 19 Jun 2014
US 8,659,935 B2Parent of this continuation
US 2011/0134683 A1Published application
US 2013/0140558 A1Published application
US 9,001,566 B2This patent

From the US filing history. Foreign family members aren’t listed.