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US 9,001,562 B2Granted
Semiconductor memory device including a dummy block
AssigneeRohm Co., Ltd.
InventorKazuhisa Ukai
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.
Claims8
A semiconductor memory device comprising:
- a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array;
- and
- at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use,
- wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks,
- wherein each of the plurality of element blocks is a memory cell including a select transistor and a capacitor,
- wherein a contact wiring of the capacitor extends away from the end portion of the memory array, and
- wherein the at least one dummy block includes a dummy gate formed by extending a gate of the select transistor away from the end portion of the memory array.
4 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array;
- and
- at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use,
- wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks,
- wherein each of the end-portion element blocks is a memory cell including a select transistor and a capacitor, and
- wherein a gate of the select transistor is disposed to be parallel to a contact wiring of the capacitor.
3 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array;
- and
- at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use,
- wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks,
- wherein each of the end-portion element blocks is a memory cell including a select transistor and two capacitors, and a gate of the select transistor is formed between the two contact wirings of the two capacitors.
2 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array;
- and
- at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use,
- wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks,
- wherein each of the plurality of element blocks is a memory cell including a select transistor and a capacitor, and
- wherein a length of a gate of the select transistor extending from the memory array is shorter than a length of the contact wiring extending from the memory array.
3 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array;
- and
- at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use,
- wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks,
- wherein each of the end-portion element blocks is a memory cell including a select transistor and a capacitor, and
- wherein a width of a contact wiring of the capacitor is larger than a width of a gate of the select transistor.
3 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array;
- and
- at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use,
- wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks,
- wherein each of the end-portion element blocks is a memory cell including a select transistor and a capacitor, and wherein the at least one dummy block has a mirroring form of only transistor arranged in one row or one column among the transistors of the end-portion element blocks.
2 more elements
Dependencies are inferred from the claim text.