US 9,001,559 B2Granted

Resistance change memory

OwnerMasahiro Takahashi, Akira Katayama +2inventors

InventorsMasahiro Takahashi, Akira Katayama, Dong Keun Kim, Byoung Chan Oh

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Abstract

According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Claims20

Dependent claims

A resistance change memory comprising:

a first memory cell including a resistance change element;
a word line coupled to the first memory cell, the word line being driven based on an address signal;
a first bit line coupled to the first memory cell and intersecting the word line, the first bit line being selected based on the address signal;
a first inverter including a first input terminal, a first output terminal, and first and second voltage terminals;
a second inverter including a second input terminal, a second output terminal, and third and fourth voltage terminals, the second input terminal being coupled to the first output terminal, the second output terminal being coupled to the first input terminal;
a first MOS transistor coupled to the first output terminal;
a second MOS transistor coupled to the second output terminal;
a third MOS transistor coupled to the first voltage terminal;
a fourth MOS transistor coupled to the third voltage terminal;
a fifth MOS transistor having a current path, one end of which is coupled to the first voltage terminal, the fifth MOS transistor having a gate supplied with a first signal;
a second bit line coupled to another end of the current path;
and
a sixth MOS transistor coupled between the second bit line and the first bit line, the sixth MOS transistor having a gate supplied with a second signal,
wherein before the sixth MOS transistor is turned on by the second signal, the fifth MOS transistor is turned on by the first signal.

11 more elements

A resistance change memory comprising:

a first memory cell including a resistance change element;
a word line coupled to the first memory cell, the word line being driven based on an address signal;
a first bit line coupled to the first memory cell and intersecting the word line, the first bit line being selected based on the address signal;
a first inverter having a first input terminal, a first output terminal, and first and second voltage terminals;
a second inverter having a second input terminal, a second output terminal, and third and fourth voltage terminals, the second input terminal being coupled to the first output terminal, the second output terminal being coupled to the first input terminal;
a first MOS transistor coupled to the first output terminal;
a second MOS transistor coupled to the second output terminal;
a third MOS transistor coupled to the first voltage terminal;
a fourth MOS transistor coupled to the third voltage terminal;
a fifth MOS transistor having a current path, one end of which is coupled to a gate of the third MOS transistor, the fifth MOS transistor having a gate supplied with a first signal;
a second bit line coupled to another end of the current path of the fifth MOS transistor;
and
a sixth MOS transistor coupled between the second bit line and the first bit line, the sixth MOS transistor having a gate supplied with a second signal,
wherein before the sixth MOS transistor is turned on by the second signal, the fifth MOS transistor is turned on by the first signal.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/018,242Filed 4 Sep 2013 · us provisional application
Priority: 22 Mar 2013
Published: US 2014/0286081 A125 Sep 2014
Granted: 7 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.