Loading patent…
AssigneesForschungszentrum Juelich GmbH, Rheinisch-Westfaelische Technische Hochschule Aachen (RWTH)
InventorsRoland Daniel Rosezin, Florian Lentz, Rainer Bruchhaus, Eike Linn, Ilia Valov, Rainer Waser, Stefan Tappertzhofen, Lutz Nielen
Estimating the term…
A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.
A method for reading out a memory element, which comprises a series connection of at least two memory cells A and B, each having a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance, state 0 of the memory element being coded in the combination of states A1 and B0 and state 1 of the memory element being coded in the combination of states A0 and B1, by measuring an electrical variable of the series circuit, comprising selecting an electrical variable to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A in state A1 makes a different contribution than the memory cell B in state B1.
A memory element having at least one first stable state 0 and a second stable state 1, which can be transferred into state 0 by the application of a first write voltage V0 and into state 1 by the application of a second write voltage V1, the two states 0 and 1 being manifested in differing electrical resistance values of the memory element when a read-out voltage VR is applied, the absolute value of which is smaller than the write voltages V0 and V1, the memory element comprising a series connection of at least two memory cells A and B, which have a respective stable state A0 or B0 having higher electrical resistance and a stable state A1 or B1 having lower electrical resistance, wherein the capacitances of the memory cells A and B differ by at least 10% from each other in the state combination A0 and B0 and/or in the state combination A1and B1.
Dependencies are inferred from the claim text.