Resistive devices and methods of operation thereof
AssigneeAdesto Technologies Corporation
InventorDeepak Kamalanathan
Life of this patent
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Abstract
A method of operating a resistive switching device includes applying a program stress to a two terminal resistive memory unit. The program stress is applied at a program voltage configured to change a state of the memory unit from a first state to a second state. The method further includes applying a verification/stabilization stress to the two terminal resistive memory unit. The verification/stabilization stress is applied at a verification/stabilization voltage. An erase stress is applied to the two terminal resistive memory unit. The erase stress is applied at an erase voltage configured to change a state of the memory unit from the second state to the first state. The verification/stabilization voltage is between the program voltage and the erase voltage.
Claims26
A method of operating a resistive switching device, the method comprising:
- applying a program stress to a two terminal resistive memory unit, the program stress being applied at a program voltage configured to change a state of the memory unit from a first state to a second state;
- applying a verification/stabilization stress to the two terminal resistive memory unit, the verification/stabilization stress being applied at a verification/stabilization voltage;
- and
- applying an erase stress to the two terminal resistive memory unit, the erase stress being applied at an erase voltage configured to change a state of the memory unit from the second state to the first state, wherein the verification/stabilization voltage is between the program voltage and the erase voltage.
A method of operating a resistive switching device, the method comprising:
- applying a program stress to a two terminal resistive memory unit, the program stress being applied at a program voltage configured to change a state of the memory unit from a first state to a second state;
- after applying the program stress, applying a read stress to the two terminal resistive memory unit, the read stress being applied at a read voltage;
- and
- after applying the read stress, applying a verification/stabilization stress to the two terminal resistive memory unit, the verification/stabilization stress being applied at a verification/stabilization voltage, wherein the verification/stabilization voltage is between the read voltage of the two terminal resistive memory unit and a erase voltage of the two terminal resistive memory unit.
A semiconductor device comprising:
- a memory cell array comprising an array of two terminal resistive memory units;
- a program circuit configured to program the array of two terminal resistive memory units;
- a verification/stabilization circuit configured to apply a verification/stabilization stress on a first memory unit of the memory cell array, the verification/stabilization stress being a voltage between a read voltage of a memory unit of the array of two terminal resistive memory units and a erase or a program voltage of a memory unit of the array of two terminal resistive memory units;
- and
- a detection circuit configured to detect a state of the first memory unit.
Dependencies are inferred from the claim text.