Blocking current leakage in a memory array

An integrated circuit, comprising:

• a memory array, the memory array including memory cells including access devices and programmable resistance memory elements coupled to the access devices, and including a plurality of modified defective memory cells in a current blocking condition;
• a redundant array, including replacement memory cells;
• and
• a redundancy table, the redundancy table mapping addresses of the plurality of modified defective memory cells in the memory array to replacement memory cells in the redundant array,
• wherein the modified defective memory cells include a modified memory element comprising phase change material and having a high resistance active region.

A method for blocking current leakage through defective memory cells in a memory array, the memory cells including access devices and programmable resistance memory elements, comprising:

• identifying addresses of defective memory cells in the memory array;
• and
• applying a modifying bias condition to modify the defective memory cells at the identified addresses, forming modified defective memory cells having a current blocking condition under bias conditions applied during operation of the array,
• wherein the memory cells include memory elements that comprise a phase change memory material having an active region which changes phase under bias conditions applied during operation of the array, and the modifying bias condition causes an electrical current pulse or pulses which induce a volume of the phase change material to adopt an amorphous phase to block current flow in the modified defective memory cell.

An automatic test system, comprising:

• a device tester adapted to identify addresses of defective memory cells in a memory array in an integrated circuit under test, and to apply a modifying bias condition to modify the defective memory cells at the identified addresses, forming modified defective memory cells having a current blocking condition under bias conditions applied during operation of the array;
• wherein the memory array includes memory cells including access devices and programmable resistance memory elements;
• wherein the integrated circuit under test includes a redundant array, including replacement memory cells, and a redundancy table, the redundancy table mapping the identified addresses of modified defective memory cells in the memory array to replacement memory cells in the redundant array;
• wherein the memory cells include memory elements that comprise a phase change memory material having an active region which changes phase under bias conditions applied during operation of the array, and the modifying bias condition causes an electrical current pulse or pulses which induce a volume of the phase change material to adopt an amorphous phase to block current flow in the modified defective memory cell.

An integrated circuit, comprising:

• a memory array, the memory array including memory cells including access devices and programmable resistance memory elements coupled to the access devices, and including a plurality of modified defective memory cells in a current blocking condition, wherein the modified defective memory cells include a modified diode in a current blocking condition for forward and reverse bias, or a modified memory element comprising phase change material and having a high resistance active region;
• a redundant array, including replacement memory cells;
• a redundancy table, the redundancy table mapping addresses of the plurality of modified defective memory cells in the memory array to replacement memory cells in the redundant array;
• and
• built-in self-test circuitry adapted to identify addresses of defective memory cells in the memory array in the integrated circuit, and to apply a modifying bias condition to modify defective memory cells at the identified addresses, forming modified defective memory cells having a current blocking condition under bias conditions applied during operation of the array, wherein the modifying bias condition is different from the bias conditions.